at91_x55.rdf

基本的几个引用程序,来看卡发的有用程序,别错过了.

# Arm.rdf
# Starting a AT91m55800a register description based off of the
# AT91r40807.rdf chip-file description provided by Atmel.
# Look for # NOT UPDATED BEGIN/END sections to know what hasn't
# been updated or checked for AT91_x55 compliance.

# NOT UPDATED BEGIN
# AT91r40807.rdf chip-file description 
# Beta test version 23/01/01  JPP : Update peripheral description
# Copyright (c) 2001 Atmel, All Rights Reserved
#
# This file contains constants for use in RDF files that describe the values
# of the AT91r40807 peripherals
# NOT UPDATED END 

rdf.version=1

############################ GHS includes ########################
~sysinclude=os_constants.rdf
~sysinclude=arm_default.rdf

######################### Top level defines ######################
~define.DEFINE_ADDR=true
~define.DEFINE_WORD=true
# hide defines are commented out, since hide doesn't for registers
# defined within a group in MULTI versions 3.5 and before.
# ~define.HIDE_ADDR=false 
# ~define.HIDE_WORD=false


group.at91x55sys.name=AT91x55: System Peripherals
group.at91x55sys.group.2=EBI
group.at91x55sys.group.4=APMC
group.at91x55sys.group.6=RTC
group.at91x55sys.group.8=WD
group.at91x55sys.group.10=AIC
group.at91x55sys.group.12=PIO
group.at91x55sys.group.14=SF
group.at91x55sys.topLevelIndex=0

group.at91x55usr.name=AT91x55: User Peripherals
group.at91x55usr.group.16=USART
group.at91x55usr.group.18=TC
group.at91x55usr.group.20=SP
group.at91x55usr.group.22=ADC
group.at91x55usr.group.24=DAC
group.at91x55usr.topLevelIndex=1

#group.EBI.topLevelIndex=2
#group.APMC.topLevelIndex=4
#group.RTC.topLevelIndex=6
#group.WD.topLevelIndex=8
#group.AIC.topLevelIndex=10
#group.PIO.topLevelIndex=12
#group.SF.topLevelIndex=14
#group.USART.topLevelIndex=16
#group.TC.topLevelIndex=18
#group.SPI.topLevelIndex=20
#group.ADC.topLevelIndex=22
#group.DAC.topLevelIndex=24


############################## EBI  ##############################

~define.EBI_BASE=0xFFE00000

group.EBI.name=EBI: External Bus Interface

group.EBI.register.25=EBI_CSR0
group.EBI.register.45=EBI_CSR1
group.EBI.register.65=EBI_CSR2
group.EBI.register.85=EBI_CSR3
group.EBI.register.105=EBI_CSR4
group.EBI.register.125=EBI_CSR5
group.EBI.register.145=EBI_CSR6
group.EBI.register.165=EBI_CSR7
group.EBI.register.185=EBI_RCR
group.EBI.register.205=EBI_MCR

##                       EBI_CSR0

#EBI_CSR0
EBI_CSR0.width=32
EBI_CSR0.access=memorymapped
EBI_CSR0.address=EBI_BASE+0x00 
EBI_CSR0.byteEndian=little
EBI_CSR0.type=bitfield

EBI_CSR0.bits.0.name=DBW
EBI_CSR0.bits.0.range=0..1
EBI_CSR0.bits.0.type=enum
EBI_CSR0.bits.0.enum.0.name=Reserved
EBI_CSR0.bits.0.enum.1.name=16 bit data bus width
EBI_CSR0.bits.0.enum.2.name=8 bit data bus width
EBI_CSR0.bits.0.enum.3.name=Reserved

EBI_CSR0.bits.1.name=WS
EBI_CSR0.bits.1.range=2..4
EBI_CSR0.bits.1.type=enum
EBI_CSR0.bits.1.enum.0.name=1 Wait State
EBI_CSR0.bits.1.enum.1.name=2 Wait States
EBI_CSR0.bits.1.enum.2.name=3 Wait States
EBI_CSR0.bits.1.enum.3.name=4 Wait States
EBI_CSR0.bits.1.enum.4.name=5 Wait States
EBI_CSR0.bits.1.enum.5.name=6 Wait States
EBI_CSR0.bits.1.enum.6.name=7 Wait States
EBI_CSR0.bits.1.enum.7.name=8 Wait States

EBI_CSR0.bits.2.name=WSE
EBI_CSR0.bits.2.range=5..5
EBI_CSR0.bits.2.type=enum
EBI_CSR0.bits.2.enum.0.name=Disable Wait States
EBI_CSR0.bits.2.enum.1.name=Enable Wait States

EBI_CSR0.bits.3.name=Reserved
EBI_CSR0.bits.3.range=6..6

EBI_CSR0.bits.4.name=PAGES
EBI_CSR0.bits.4.range=7..8
EBI_CSR0.bits.4.type=enum
EBI_CSR0.bits.4.enum.0.name=1 MB Page Size
EBI_CSR0.bits.4.enum.1.name=4 MB Page Size
EBI_CSR0.bits.4.enum.2.name=16 MB Page Size
EBI_CSR0.bits.4.enum.3.name=64 MB Page Size

EBI_CSR0.bits.5.name=TDF
EBI_CSR0.bits.5.range=9..11
EBI_CSR0.bits.5.type=enum
EBI_CSR0.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR0.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR0.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR0.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR0.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR0.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR0.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR0.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR0.bits.6.name=BAT
EBI_CSR0.bits.6.range=12..12
EBI_CSR0.bits.6.type=enum
EBI_CSR0.bits.6.enum.0.name=Byte-Write access
EBI_CSR0.bits.6.enum.1.name=Byte-Select access

EBI_CSR0.bits.7.name=CSEN
EBI_CSR0.bits.7.range=13..13
EBI_CSR0.bits.7.type=enum
EBI_CSR0.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR0.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR0.bits.8.name=WP
EBI_CSR0.bits.8.range=14..14
EBI_CSR0.bits.8.type=enum
EBI_CSR0.bits.8.enum.0.name=Not Write Protected
EBI_CSR0.bits.8.enum.1.name=Write Protected

EBI_CSR0.bits.9.name=Reserved
EBI_CSR0.bits.9.range=15..19

EBI_CSR0.bits.10.name=BA
EBI_CSR0.bits.10.range=20..31

##                       EBI_CSR1

#EBI_CSR1
EBI_CSR1.width=32
EBI_CSR1.access=memorymapped
EBI_CSR1.address=EBI_BASE+0x04 
EBI_CSR1.byteEndian=little
EBI_CSR1.type=bitfield

EBI_CSR1.bits.0.name=DBW
EBI_CSR1.bits.0.range=0..1
EBI_CSR1.bits.0.type=enum
EBI_CSR1.bits.0.enum.0.name=Reserved
EBI_CSR1.bits.0.enum.1.name=16 bit data bus width
EBI_CSR1.bits.0.enum.2.name=8 bit data bus width
EBI_CSR1.bits.0.enum.3.name=Reserved

EBI_CSR1.bits.1.name=WS
EBI_CSR1.bits.1.range=2..4
EBI_CSR1.bits.1.type=enum
EBI_CSR1.bits.1.enum.0.name=1 Wait State
EBI_CSR1.bits.1.enum.1.name=2 Wait States
EBI_CSR1.bits.1.enum.2.name=3 Wait States
EBI_CSR1.bits.1.enum.3.name=4 Wait States
EBI_CSR1.bits.1.enum.4.name=5 Wait States
EBI_CSR1.bits.1.enum.5.name=6 Wait States
EBI_CSR1.bits.1.enum.6.name=7 Wait States
EBI_CSR1.bits.1.enum.7.name=8 Wait States

EBI_CSR1.bits.2.name=WSE
EBI_CSR1.bits.2.range=5..5
EBI_CSR1.bits.2.type=enum
EBI_CSR1.bits.2.enum.0.name=Disable Wait States
EBI_CSR1.bits.2.enum.1.name=Enable Wait States

EBI_CSR1.bits.3.name=Reserved
EBI_CSR1.bits.3.range=6..6

EBI_CSR1.bits.4.name=PAGES
EBI_CSR1.bits.4.range=7..8
EBI_CSR1.bits.4.type=enum
EBI_CSR1.bits.4.enum.0.name=1 MB Page Size
EBI_CSR1.bits.4.enum.1.name=4 MB Page Size
EBI_CSR1.bits.4.enum.2.name=16 MB Page Size
EBI_CSR1.bits.4.enum.3.name=64 MB Page Size

EBI_CSR1.bits.5.name=TDF
EBI_CSR1.bits.5.range=9..11
EBI_CSR1.bits.5.type=enum
EBI_CSR1.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR1.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR1.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR1.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR1.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR1.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR1.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR1.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR1.bits.6.name=BAT
EBI_CSR1.bits.6.range=12..12
EBI_CSR1.bits.6.type=enum
EBI_CSR1.bits.6.enum.0.name=Byte-Write access
EBI_CSR1.bits.6.enum.1.name=Byte-Select access

EBI_CSR1.bits.7.name=CSEN
EBI_CSR1.bits.7.range=13..13
EBI_CSR1.bits.7.type=enum
EBI_CSR1.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR1.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR1.bits.8.name=WP
EBI_CSR1.bits.8.range=14..14
EBI_CSR1.bits.8.type=enum
EBI_CSR1.bits.8.enum.0.name=Not Write Protected
EBI_CSR1.bits.8.enum.1.name=Write Protected

EBI_CSR1.bits.9.name=Reserved
EBI_CSR1.bits.9.range=15..19

EBI_CSR1.bits.10.name=BA
EBI_CSR1.bits.10.range=20..31

##                       EBI_CSR2

#EBI_CSR2
EBI_CSR2.width=32
EBI_CSR2.access=memorymapped
EBI_CSR2.address=EBI_BASE+0x08 
EBI_CSR2.byteEndian=little
EBI_CSR2.type=bitfield

EBI_CSR2.bits.0.name=DBW
EBI_CSR2.bits.0.range=0..1
EBI_CSR2.bits.0.type=enum
EBI_CSR2.bits.0.enum.0.name=Reserved
EBI_CSR2.bits.0.enum.1.name=16 bit data bus width
EBI_CSR2.bits.0.enum.2.name=8 bit data bus width
EBI_CSR2.bits.0.enum.3.name=Reserved

EBI_CSR2.bits.1.name=WS
EBI_CSR2.bits.1.range=2..4
EBI_CSR2.bits.1.type=enum
EBI_CSR2.bits.1.enum.0.name=1 Wait State
EBI_CSR2.bits.1.enum.1.name=2 Wait States
EBI_CSR2.bits.1.enum.2.name=3 Wait States
EBI_CSR2.bits.1.enum.3.name=4 Wait States
EBI_CSR2.bits.1.enum.4.name=5 Wait States
EBI_CSR2.bits.1.enum.5.name=6 Wait States
EBI_CSR2.bits.1.enum.6.name=7 Wait States
EBI_CSR2.bits.1.enum.7.name=8 Wait States

EBI_CSR2.bits.2.name=WSE
EBI_CSR2.bits.2.range=5..5
EBI_CSR2.bits.2.type=enum
EBI_CSR2.bits.2.enum.0.name=Disable Wait States
EBI_CSR2.bits.2.enum.1.name=Enable Wait States

EBI_CSR2.bits.3.name=Reserved
EBI_CSR2.bits.3.range=6..6

EBI_CSR2.bits.4.name=PAGES
EBI_CSR2.bits.4.range=7..8
EBI_CSR2.bits.4.type=enum
EBI_CSR2.bits.4.enum.0.name=1 MB Page Size
EBI_CSR2.bits.4.enum.1.name=4 MB Page Size
EBI_CSR2.bits.4.enum.2.name=16 MB Page Size
EBI_CSR2.bits.4.enum.3.name=64 MB Page Size

EBI_CSR2.bits.5.name=TDF
EBI_CSR2.bits.5.range=9..11
EBI_CSR2.bits.5.type=enum
EBI_CSR2.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR2.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR2.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR2.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR2.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR2.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR2.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR2.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR2.bits.6.name=BAT
EBI_CSR2.bits.6.range=12..12
EBI_CSR2.bits.6.type=enum
EBI_CSR2.bits.6.enum.0.name=Byte-Write access
EBI_CSR2.bits.6.enum.1.name=Byte-Select access

EBI_CSR2.bits.7.name=CSEN
EBI_CSR2.bits.7.range=13..13
EBI_CSR2.bits.7.type=enum
EBI_CSR2.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR2.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR2.bits.8.name=WP
EBI_CSR2.bits.8.range=14..14
EBI_CSR2.bits.8.type=enum
EBI_CSR2.bits.8.enum.0.name=Not Write Protected
EBI_CSR2.bits.8.enum.1.name=Write Protected

EBI_CSR2.bits.9.name=Reserved
EBI_CSR2.bits.9.range=15..19

EBI_CSR2.bits.10.name=BA
EBI_CSR2.bits.10.range=20..31

##                       EBI_CSR3

#EBI_CSR3
EBI_CSR3.width=32
EBI_CSR3.access=memorymapped
EBI_CSR3.address=EBI_BASE+0x0c 
EBI_CSR3.byteEndian=little
EBI_CSR3.type=bitfield

EBI_CSR3.bits.0.name=DBW
EBI_CSR3.bits.0.range=0..1
EBI_CSR3.bits.0.type=enum
EBI_CSR3.bits.0.enum.0.name=Reserved
EBI_CSR3.bits.0.enum.1.name=16 bit data bus width
EBI_CSR3.bits.0.enum.2.name=8 bit data bus width
EBI_CSR3.bits.0.enum.3.name=Reserved

EBI_CSR3.bits.1.name=WS
EBI_CSR3.bits.1.range=2..4
EBI_CSR3.bits.1.type=enum
EBI_CSR3.bits.1.enum.0.name=1 Wait State
EBI_CSR3.bits.1.enum.1.name=2 Wait States
EBI_CSR3.bits.1.enum.2.name=3 Wait States
EBI_CSR3.bits.1.enum.3.name=4 Wait States
EBI_CSR3.bits.1.enum.4.name=5 Wait States
EBI_CSR3.bits.1.enum.5.name=6 Wait States
EBI_CSR3.bits.1.enum.6.name=7 Wait States
EBI_CSR3.bits.1.enum.7.name=8 Wait States

EBI_CSR3.bits.2.name=WSE
EBI_CSR3.bits.2.range=5..5
EBI_CSR3.bits.2.type=enum
EBI_CSR3.bits.2.enum.0.name=Disable Wait States
EBI_CSR3.bits.2.enum.1.name=Enable Wait States

EBI_CSR3.bits.3.name=Reserved
EBI_CSR3.bits.3.range=6..6

EBI_CSR3.bits.4.name=PAGES
EBI_CSR3.bits.4.range=7..8
EBI_CSR3.bits.4.type=enum
EBI_CSR3.bits.4.enum.0.name=1 MB Page Size
EBI_CSR3.bits.4.enum.1.name=4 MB Page Size
EBI_CSR3.bits.4.enum.2.name=16 MB Page Size
EBI_CSR3.bits.4.enum.3.name=64 MB Page Size

EBI_CSR3.bits.5.name=TDF
EBI_CSR3.bits.5.range=9..11
EBI_CSR3.bits.5.type=enum
EBI_CSR3.bits.5.enum.0.name=0 Cycles after transfer
EBI_CSR3.bits.5.enum.1.name=1 Cycles after transfer
EBI_CSR3.bits.5.enum.2.name=2 Cycles after transfer
EBI_CSR3.bits.5.enum.3.name=3 Cycles after transfer
EBI_CSR3.bits.5.enum.4.name=4 Cycles after transfer
EBI_CSR3.bits.5.enum.5.name=5 Cycles after transfer
EBI_CSR3.bits.5.enum.6.name=6 Cycles after transfer
EBI_CSR3.bits.5.enum.7.name=7 Cycles after transfer

EBI_CSR3.bits.6.name=BAT
EBI_CSR3.bits.6.range=12..12
EBI_CSR3.bits.6.type=enum
EBI_CSR3.bits.6.enum.0.name=Byte-Write access
EBI_CSR3.bits.6.enum.1.name=Byte-Select access

EBI_CSR3.bits.7.name=CSEN
EBI_CSR3.bits.7.range=13..13
EBI_CSR3.bits.7.type=enum
EBI_CSR3.bits.7.enum.0.name=Chip Select Disabled
EBI_CSR3.bits.7.enum.1.name=Chip Select Enabled

EBI_CSR3.bits.8.name=WP
EBI_CSR3.bits.8.range=14..14
EBI_CSR3.bits.8.type=enum
EBI_CSR3.bits.8.enum.0.name=Not Write Protected
EBI_CSR3.bits.8.enum.1.name=Write Protected

EBI_CSR3.bits.9.name=Reserved
EBI_CSR3.bits.9.range=15..19

EBI_CSR3.bits.10.name=BA
EBI_CSR3.bits.10.range=20..31