fg439_pwm_adc_subroutine.s43

TI MSP430针对cap sense 按键的源码, 可实现单击或滑动键, 如IPOD上的人机接口.

;  MSP430xG439 software ADC demo
;
;  Description: This codes generates a PWM signal, and adjusts its ratio until a heavily low pass
;               filtered version of the signal (i.e. its equivalent DC value) matches a DC signal to
;               be measured. The match is detected using comparator A.
;
;                                T.I.
;                           MSP430xG43x MCU
;
;                           ---------------
;                          |               |
; signal to be measured--->|CA1            |
;                          |               |
;                   +-470k-|P2.0        XIN|----+
;                   |      |               |  -----
;                   +----- |CA0            | 327688Hz
;                   |      |               |  -----
;                  ===.047 |           XOUT|----+
;                   |      |               |
;                   ------ |VSS            |
;                          |               |
;                           ---------------
;
;   Vincent Chan
;   Texas Instruments, Inc
;   Aug 2002
;***************************************************************************

#include  "msp430xG43x.h"

;-----------------------------------------------------------------------------
            RSEG    CODE
;-----------------------------------------------------------------------------

PUBLIC      _Meas_ADC
PUBLIC       Meas_ADC
;            CPU registers used
#define      ADCData  R11
#define      DAC_Out  R13
;---------------------------------------------------------------------------
_Meas_ADC
Meas_ADC;    Subroutine: Meaure A/D Converter, BCD A/D Result --> ADCData
;            R15 used as working register and not saved
;---------------------------------------------------------------------------
             push    R15
             push    DAC_Out
             push    ADCData

             mov.b   #CAON,&CACTL1          ; Comparator on
             mov     #BIT0,DAC_Out          ;
             clr     ADCData                ; Clear ADCData register
             call    #Prime_n_Sample_ADC    ; Sample --> ADCData
             call    #Sample_ADC            ; Sample --> ADCData+Previous
Meas_Over    clr.b   &CACTL1                ; Comparator off

             mov     ADCData,R12            ;R12 is the return value

             pop     ADCData
             pop     DAC_Out
             pop     R15

             ret


Prime_n_Sample_ADC
Prime_ADC
             mov    #1000,R15
P_Test_DAC   bit.b  #CAOUT,&CACTL2          ; Comparator hi/low?
             jnc    P_Low1                  ; Jump --> Low

P_High
             bic.b  DAC_Out,&P2OUT          ; Reset power to capacitor
             jmp    P_Meas_                 ;
P_Low1
             bis.b  DAC_Out,&P2OUT          ; Set power to capacitor
             setc                           ;
             mov    ADCData,ADCData         ; keep constant the same
P_Meas_      dec    R15                     ; Decrement Loop Count
             jnz    P_Test_DAC


Sample_ADC   mov    &VCC_Cal,R15            ; ~3300
             rra    R15                     ; VCC/2
Test_DAC     bit.b  #CAOUT,&CACTL2          ; Comparator hi/low?
             jnc    Low1                    ; Jump --> Low
High_        bic.b  DAC_Out,&P2OUT          ; Reset power to capacitor
             jmp    Meas_                   ;
Low1         bis.b  DAC_Out,&P2OUT          ; Set power to capacitor
             setc                           ;
             adc    ADCData

Meas_        dec    R15                     ; Decrement Loop Count
             jnz    Test_DAC                ; Measurement Loop Over?
             bic.b  DAC_Out,&P2OUT          ; Reset power to capacitor
             xor.b  #CAEX,&CACTL1           ; invert comparator terminals

             ret                            ; Return from Subroutine
                                            ;



             RSEG INFO

VCC_Cal      DW      02800                   ; Actual system VCC
                                            ;

             END