counters.c

一个内存数据库的源代码这是服务器端还有客户端

	{33, 33, (str) &chr_nil, "Instruction fetch stall cycles", 0x87, 0},	/* K7_instr_fetch_stall               , "instr_fetch_stall"               , 33 , 25 , K7_INSTRUCTION_FETCH_STALL_CYCLES                             , */
	{34, 34, (str) &chr_nil, "Return stack hits", 0x88, 0},	/* K7_rtrn_stack_hits                 , "rtrn_stack_hits"                 , 34 , 26 , K7_RETURN_STACK_HITS                                          , */
	{35, 35, (str) &chr_nil, "Return stack overflow", 0x89, 0},	/* K7_rtrn_stack_overflow             , "rtrn_stack_overflow"             , 35 , 27 , K7_RETURN_STACK_OVERFLOW                                      , */
	{36, 36, (str) &chr_nil, "Retired near returns", 0xC8, 0},	/* K7_near_rtrn_retired               , "near_rtrn_retired"               , 36 , 36 , K7_RETIRED_NEAR_RETURNS                                       , */
	{37, 37, (str) &chr_nil, "Retired near returns mispredicted", 0xC9, 0},	/* K7_near_rtrn_miss_pred_retired     , "near_rtrn_miss_pred_retired"     , 37 , 37 , K7_RETIRED_NEAR_RETURNS_MISPREDICTED                          , */
	{38, 38, (str) &chr_nil, "Retired indirect branches with target mispredicted", 0xCA, 0},	/* K7_ind_br_target_miss_pred_retired , "ind_br_target_miss_pred_retired" , 38 , 38 , K7_RETIRED_INDIRECT_BRANCHES_WITH_TARGET_MISPREDICTED         , */
	{39, 39, (str) &chr_nil, "Interrupts asked while pending cycles", 0xCE, 0},	/* K7_cyc_int_masked_pending          , "cyc_int_masked_pending"          , 39 , 40 , K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES                     , */
	{40, 40, (str) &chr_nil, "Instruction decoder empty", 0xD0, 0},	/* K7_instr_dec_empty                 , "instr_dec_empty"                 , 40 , 42 , K7_INSTRUCTION_DECODER_EMPTY                                  , */
	{41, 41, (str) &chr_nil, "Dispatch stalls", 0xD1, 0},	/* K7_dispatch_stall                  , "dispatch_stall"                  , 41 , 43 , K7_DISPATCH_STALLS                                            , */
	{42, 42, (str) &chr_nil, "Branch aborts to retire", 0xD2, 0},	/* K7_br_aborts_retire                , "br_aborts_retire"                , 42 , 44 , K7_BRANCH_ABORTS_TO_RETIRE                                    , */
	{43, 43, (str) &chr_nil, "Serialize", 0xD3, 0},	/* K7_serialize                       , "serialize"                       , 43 , 45 , K7_SERIALIZE                                                  , */
	{44, 44, (str) &chr_nil, "Segment load stall", 0xD4, 0},	/* K7_seg_load_stall                  , "seg_load_stall"                  , 44 , 46 , K7_SEGMENT_LOAD_STALL                                         , */
	{45, 45, (str) &chr_nil, "ICU full", 0xD5, 0},	/* K7_ICU_full                        , "ICU_full"                        , 45 , 47 , K7_ICU_FULL                                                   , */
	{46, 46, (str) &chr_nil, "Reservation stations full", 0xD6, 0},	/* K7_res_stations_full               , "res_stations_full"               , 46 , 48 , K7_RESERVATION_STATIONS_FULL                                  , */
	{47, 47, (str) &chr_nil, "FPU full", 0xD7, 0},	/* K7_FPU_full                        , "FPU_full"                        , 47 , 49 , K7_FPU_FULL                                                   , */
	{48, 48, (str) &chr_nil, "LS full", 0xD8, 0},	/* K7_LS_full                         , "LS_full"                         , 48 , 50 , K7_LS_FULL                                                    , */
	{49, 49, (str) &chr_nil, "All quiet stall", 0xD9, 0},	/* K7_all_quiet_stall                 , "all_quiet_stall"                 , 49 , 51 , K7_ALL_QUIET_STALL                                            , */
	{50, 50, (str) &chr_nil, "Far transfer or resync branch pending", 0xDA, 0},	/* K7_far_tf_rs_br_pending            , "far_tf_rs_br_pending"            , 50 , 52 , K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING                      , */
	{51, 51, (str) &chr_nil, "Breakpoint matches for DR0", 0xDC, 0},	/* K7_brk_pnt_DR0                     , "brk_pnt_DR0"                     , 51 , 53 , K7_BREAKPOINT_MATCHES_FOR_DR0                                 , */
	{52, 52, (str) &chr_nil, "Breakpoint matches for DR1", 0xDD, 0},	/* K7_brk_pnt_DR1                     , "brk_pnt_DR1"                     , 52 , 54 , K7_BREAKPOINT_MATCHES_FOR_DR1                                 , */
	{53, 53, (str) &chr_nil, "Breakpoint matches for DR2", 0xDE, 0},	/* K7_brk_pnt_DR2                     , "brk_pnt_DR2"                     , 53 , 55 , K7_BREAKPOINT_MATCHES_FOR_DR2                                 , */
	{54, 54, (str) &chr_nil, "Breakpoint matches for DR3", 0xDF, 0},	/* K7_brk_pnt_DR3                     , "brk_pnt_DR3"                     , 54 , 56 , K7_BREAKPOINT_MATCHES_FOR_DR3                                 , */
	{55, 55, "L1_inst_misses", "Instruction cache refills from L2", 0x82, 0},	/* 0                                  , "IC_REFILLS_FROM_L2"              , -1 , 20 , K7_INSTRUCTION_CACHE_REFILLS_FROM_L2                          , */
	{56, 56, "L2_inst_misses", "Instruction cache refills from System", 0x83, 0},	/* 0                                  , "IC_REFILLS_FROM_SYSTEM"          , -1 , 21 , K7_INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM                      , */
	{29, 29, (str) &chr_nil, (str) &chr_nil, 0x76, 0}
};

  /* K8 (x86_64) Opteron */

#define K8_NUMEVENTS 79
event_t K8_event[K8_NUMEVENTS + 1] = {
	{ 0,  0, (str) &chr_nil, "K7_DATA_CACHE_ACCESSES", 0x40, 0},
	{ 1,  1, (str) &chr_nil, "K7_DATA_CACHE_MISSES", 0x41, 0},
	{ 2,  2, "L1_data_misses", "K7_DATA_CACHE_REFILLS_FROM_L2", 0x42, 0},
	{ 3,  3, "L2_data_misses", "K7_DATA_CACHE_REFILLS_FROM_SYSTEM", 0x43, 0},
	{ 4,  4, (str) &chr_nil, "K7_DATA_CACHE_WRITEBACKS", 0x44, 0},
	{ 5,  5, "TLB_misses",   "K7_L1_DTLB_MISSES_AND_L2_DTLB_HITS", 0x45, 0},
	{ 6,  6, (str) &chr_nil, "K7_L1_AND_L2_DTLB_MISSES", 0x46, 0},
	{ 7,  7, (str) &chr_nil, "K7_MISALIGNED_DATA_REFERENCES", 0x47, 0},
	{ 8,  8, (str) &chr_nil, "K7_INSTRUCTION_CACHE_FETCHES", 0x80, 0},
	{ 9,  9, (str) &chr_nil, "K7_INSTRUCTION_CACHE_MISSES", 0x81, 0},
	{10, 10, "iTLB_misses", "K7_L1_ITLB_MISSES_AND_L2_ITLB_HITS", 0x84, 0},
	{11, 11, (str) &chr_nil, "K7_L1_AND_L2_ITLB_MISSES", 0x85, 0},
	{12, 12, (str) &chr_nil, "K7_RETIRED_INSTRUCTIONS", 0xC0, 0},
	{13, 13, (str) &chr_nil, "K7_RETIRED_OPS", 0xC1, 0},
	{14, 14, "branches", "K7_RETIRED_BRANCHES", 0xC2, 0},
	{15, 15, "branch_misses", "K7_RETIRED_BRANCHES_MISPREDICTED", 0xC3, 0},
	{16, 16, "Tbranches", "K7_RETIRED_TAKEN_BRANCHES", 0xC4, 0},
	{17, 17, "Tbranch_misses", "K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED", 0xC5, 0},
	{18, 18, (str) &chr_nil, "K7_RETIRED_FAR_CONTROL_TRANSFERS", 0xC6, 0},
	{19, 19, (str) &chr_nil, "K7_RETIRED_RESYNC_BRANCHES", 0xC7, 0},
	{20, 20, (str) &chr_nil, "K7_INTERRUPTS_MASKED_CYCLES", 0xCD, 0},
	{21, 21, (str) &chr_nil, "K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES", 0xCE, 0},
	{22, 22, (str) &chr_nil, "K7_NUMBER_OF_TAKEN_HARDWARE_INTERRUPTS", 0xCF, 0},
	{23, 23, (str) &chr_nil, "K8_DISPATCHED_FPU_OPS", 0x00, 0},
	{24, 24, (str) &chr_nil, "K8_NO_FPU_OPS", 0x01, 0},
	{25, 25, (str) &chr_nil, "K8_FAST_FPU_OPS", 0x02, 0},
	{26, 26, (str) &chr_nil, "K8_SEG_REG_LOAD", 0x20, 0},
	{27, 27, (str) &chr_nil, "K8_SELF_MODIFY_RESYNC", 0x21, 0},
	{28, 28, (str) &chr_nil, "K8_LS_RESYNC_BY_SNOOP", 0x22, 0},
	{29, 29, (str) &chr_nil, "K8_LS_BUFFER_FULL", 0x23, 0},
	{30, 30, (str) &chr_nil, "K8_OP_LATE_CANCEL", 0x25, 0},
	{31, 31, (str) &chr_nil, "K8_CFLUSH_RETIRED", 0x26, 0},
	{32, 32, (str) &chr_nil, "K8_CPUID_RETIRED", 0x27, 0},
	{33, 33, (str) &chr_nil, "K8_ACCESS_CANCEL_LATE", 0x48, 0},
	{34, 34, (str) &chr_nil, "K8_ACCESS_CANCEL_EARLY", 0x49, 0},
	{35, 35, (str) &chr_nil, "K8_ECC_BIT_ERR", 0x4A, 0},
	{36, 36, (str) &chr_nil, "K8_DISPATCHED_PRE_INSTRS", 0x4B, 0},
	{37, 37, "cycles", "K8_CPU_CLK_UNHALTED", 0x76, 0},
	{38, 38, (str) &chr_nil, "K8_BU_INT_L2_REQ", 0x7D, 0},
	{39, 39, (str) &chr_nil, "K8_BU_FILL_REQ", 0x7E, 0},
	{40, 40, (str) &chr_nil, "K8_BU_FILL_L2", 0x7F, 0},
	{41, 41, "L1_inst_misses", "K8_IC_REFILL_FROM_L2", 0x82, 0},
	{42, 42, "L2_inst_misses", "K8_IC_REFILL_FROM_SYS", 0x83, 0},
	{43, 43, (str) &chr_nil, "K8_IC_RESYNC_BY_SNOOP", 0x86, 0},
	{44, 44, (str) &chr_nil, "K8_IC_FETCH_STALL", 0x87, 0},
	{45, 45, (str) &chr_nil, "K8_IC_STACK_HIT", 0x88, 0},
	{46, 46, (str) &chr_nil, "K8_IC_STACK_OVERFLOW", 0x89, 0},
	{47, 47, (str) &chr_nil, "K8_RETIRED_NEAR_RETURNS", 0xC8, 0},
	{48, 48, (str) &chr_nil, "K8_RETIRED_RETURNS_MISPREDICT", 0xC9, 0},
	{49, 49, (str) &chr_nil, "K8_RETIRED_BRANCH_MISCOMPARE", 0xCA, 0},
	{50, 50, (str) &chr_nil, "K8_RETIRED_FPU_INSTRS", 0xCB, 0},
	{51, 51, (str) &chr_nil, "K8_RETIRED_FASTPATH_INSTRS", 0xCC, 0},
	{52, 52, (str) &chr_nil, "K8_DECODER_EMPTY", 0xD0, 0},
	{53, 53, (str) &chr_nil, "K8_DISPATCH_STALLS", 0xD1, 0},
	{54, 54, (str) &chr_nil, "K8_DISPATCH_STALL_FROM_BRANCH_ABORT", 0xD2, 0},
	{55, 55, (str) &chr_nil, "K8_DISPATCH_STALL_SERIALIZATION", 0xD3, 0},
	{56, 56, (str) &chr_nil, "K8_DISPATCH_STALL_SEG_LOAD", 0xD4, 0},
	{57, 57, (str) &chr_nil, "K8_DISPATCH_STALL_REORDER_BUFFER", 0xD5, 0},
	{58, 58, (str) &chr_nil, "K8_DISPATCH_STALL_RESERVE_STATIONS", 0xD6, 0},
	{59, 59, (str) &chr_nil, "K8_DISPATCH_STALL_FPU", 0xD7, 0},
	{60, 60, (str) &chr_nil, "K8_DISPATCH_STALL_LS", 0xD8, 0},
	{61, 61, (str) &chr_nil, "K8_DISPATCH_STALL_QUIET_WAIT", 0xD9, 0},
	{62, 62, (str) &chr_nil, "K8_DISPATCH_STALL_PENDING", 0xDA, 0},
	{63, 63, (str) &chr_nil, "K8_FPU_EXCEPTIONS", 0xDB, 0},
	{64, 64, (str) &chr_nil, "K8_DR0_BREAKPOINTS", 0xDC, 0},
	{65, 65, (str) &chr_nil, "K8_DR1_BREAKPOINTS", 0xDD, 0},
	{66, 66, (str) &chr_nil, "K8_DR2_BREAKPOINTS", 0xDE, 0},
	{67, 67, (str) &chr_nil, "K8_DR3_BREAKPOINTS", 0xDF, 0},
	{68, 68, (str) &chr_nil, "K8_MEM_PAGE_ACCESS", 0xE0, 0},
	{69, 69, (str) &chr_nil, "K8_MEM_PAGE_TBL_OVERFLOW", 0xE1, 0},
	{70, 70, (str) &chr_nil, "K8_DRAM_SLOTS_MISSED", 0xE2, 0},
	{71, 71, (str) &chr_nil, "K8_MEM_TURNAROUND", 0xE3, 0},
	{72, 72, (str) &chr_nil, "K8_MEM_BYPASS_SAT", 0xE4, 0},
	{73, 73, (str) &chr_nil, "K8_SIZED_COMMANDS", 0xEB, 0},
	{74, 74, (str) &chr_nil, "K8_PROBE_RESULT", 0xEC, 0},
	{75, 75, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS0_WIDTH", 0xF6, 0},
	{76, 76, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS1_WIDTH", 0xF7, 0},
	{77, 77, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS2_WIDTH", 0xF8, 0},
	{78, 78, (str) &chr_nil, "K8_LOCKED_OP", 0x24, 0},
	{37, 37, (str) &chr_nil, (str) &chr_nil, 0x76, 0}
};

/* P4 */
#define P4_NUMEVENTS 49
event_t P4_event[P4_NUMEVENTS + 1] = {
	/* default pefctr configurations */
	{ 0, 0, (str) &chr_nil, "P4_TC_DELIVER_MODE", 0, 0 },
	{ 1, 1, (str) &chr_nil, "P4_BPU_FETCH_REQUEST", 1, 0 },
	{ 2, 2, (str) &chr_nil, "P4_ITLB_REFERENCE", 2, 0 },
	{ 3, 3, (str) &chr_nil, "P4_MEMORY_CANCEL", 3, 0 },
	{ 4, 4, (str) &chr_nil, "P4_MEMORY_COMPLETE", 4, 0 },
	{ 5, 5, (str) &chr_nil, "P4_LOAD_PORT_REPLAY", 5, 0 },
	{ 6, 6, (str) &chr_nil, "P4_STORE_PORT_REPLAY", 6, 0 },
	{ 7, 7, (str) &chr_nil, "P4_MOB_LOAD_REPLAY", 7, 0 },
	{ 8, 8, (str) &chr_nil, "P4_PAGE_WALK_TYPE", 8, 0 },
	{ 9, 9, (str) &chr_nil, "P4_BSQ_CACHE_REFERENCE", 9, 0 },
	{ 10, 10, (str) &chr_nil, "P4_IOQ_ALLOCATION", 10, 0 },
	{ 11, 11, (str) &chr_nil, "P4_IOQ_ACTIVE_ENTRIES", 11, 0 },
	{ 12, 12, (str) &chr_nil, "P4_FSB_DATA_ACTIVITY", 12, 0 },
	{ 13, 13, (str) &chr_nil, "P4_BSQ_ALLOCATION", 13, 0 },
	{ 14, 14, (str) &chr_nil, "P4_BSQ_ACTIVE_ENTRIES", 14, 0 },
	{ 15, 15, (str) &chr_nil, "P4_SSE_INPUT_ASSIST", 15, 0 },
	{ 16, 16, (str) &chr_nil, "P4_PACKED_SP_UOP", 16, 0 },
	{ 17, 17, (str) &chr_nil, "P4_PACKED_DP_UOP", 17, 0 },
	{ 18, 18, (str) &chr_nil, "P4_SCALAR_SP_UOP", 18, 0 },
	{ 19, 19, (str) &chr_nil, "P4_SCALAR_DP_UOP", 19, 0 },
	{ 20, 20, (str) &chr_nil, "P4_64BIT_MMX_UOP", 20, 0 },
	{ 21, 21, (str) &chr_nil, "P4_128BIT_MMX_UOP", 21, 0 },
	{ 22, 22, (str) &chr_nil, "P4_X87_FP_UOP", 22, 0 },
	{ 23, 23, (str) &chr_nil, "P4_X87_SIMD_MOVES_UOP", 23, 0 },
	{ 24, 24, (str) &chr_nil, "P4_TC_MISC", 24, 0 },
	{ 25, 25, (str) &chr_nil, "P4_GLOBAL_POWER_EVENTS", 25, 0 },
	{ 26, 26, (str) &chr_nil, "P4_TC_MS_XFER", 26, 0 },
	{ 27, 27, (str) &chr_nil, "P4_UOP_QUEUE_WRITES", 27, 0 },