counters.c

一个内存数据库的源代码这是服务器端还有客户端

	{36, 36, (str) &chr_nil, "breakpoint_matches_on_DR3", 0x26, 0},	/* P5_BRK_DR3               , "brk_dr3"               , 36 , 34 , P5_BREAKPOINT_MATCH_ON_DR3_REGISTER            , */
	{37, 37, (str) &chr_nil, "hardware_interrupts", 0x27, 0},	/* P5_HDW_INT               , "hdw_int"               , 37 , 35 , P5_HARDWARE_INTERRUPTS                         , */
	{38, 38, (str) &chr_nil, "data_reads_or_writes", 0x28, 0},	/* P5_MEM_READ_WRITE_HIT    , "mem_read_write_hit"    , 38 , 36 , P5_DATA_READ_OR_WRITE                          , */
	{39, 39, "L1_data_misses", "data_read/write_misses", 0x29, 0},	/* P5_MEM_READ_WRITE_MISS   , "mem_read_write_miss"   , 39 , 37 , P5_DATA_READ_MISS_OR_WRITE_MISS                , */
	{22, 22, (str) &chr_nil, (str) &chr_nil, 0x16, 0}
};

  /* P6 (i686) PentiumPro/PentiumII/PentiumIII/Celeron */

#if defined(HAVE_LIBPERFCTR)
typedef union {
	unsigned int word;	/* to initialize in one assignment */
	struct p6_k7_cesr {
		unsigned int evsel:8;	/* event select */
		unsigned int umask:8;	/* further qualifies event (MESI) */
		unsigned int usr:1;	/* count in user mode (CPL=1,2,3) */
		unsigned int os:1;	/* count in os mode (CPL=0) */
		unsigned int e:1;	/* edge detect */
		unsigned int pc:1;	/* pin control */
		unsigned int aint:1;	/* local APIC interrupt enable on overflow */
		unsigned int res:1;	/* reserved */
		unsigned int en:1;	/* enable counters (P6: sel0 only!) */
		unsigned int inv:1;	/* invert counter mask */
		unsigned int cmask:8;	/* if!0, compare with events */
	} cesr;
} P6_K7_cesr_t;

	/* defaults:
	 * P6_K7_cesr0.cesr.usr = P6_K7_cesr1.cesr.usr = 1; (count in user mode, only)
	 * P6_K7_cesr0.cesr.en  = P6_K7_cesr1.cesr.en  = 1;
	 */
P6_K7_cesr_t P6_K7_cesr0 = { ((1 << 16) | (1 << 22)) }, P6_K7_cesr1 = {
((1 << 16) | (1 << 22))};
#endif

#define P6_NUMEVENTS 68
event_t P6_event[P6_NUMEVENTS + 1] = {
	{0, 0, (str) &chr_nil, "all_memory_references,_cachable_and_non", 0x43, 0},	/* P6_DATA_MEM_REFS                 , "data_mem_refs"                 , P6_DATA_MEM_REFS                 , */
	{1, 1, "L1_data_misses", "total_lines_allocated_in_the_DCU", 0x45, 0},	/* P6_DCU_LINES_IN                  , "dcu_lines_in"                  , P6_DCU_LINES_IN                  , */
	{2, 2, (str) &chr_nil, "number_of_M_state_lines_allocated_in_DCU", 0x46, 0},	/* P6_DCU_M_LINES_IN                , "dcu_m_lines_in"                , P6_DCU_M_LINES_IN                , */
	{3, 3, (str) &chr_nil, "number_of_M_lines_evicted_from_the_DCU", 0x47, 0},	/* P6_DCU_M_LINES_OUT               , "dcu_m_lines_out"               , P6_DCU_M_LINES_OUT               , */
	{4, 4, (str) &chr_nil, "number_of_cycles_while_DCU_miss_outstanding", 0x48, 0},	/* P6_DCU_MISS_OUTSTANDING          , "dcu_miss_outstanding"          , P6_DCU_MISS_OUTSTANDING          , */
	{5, 5, (str) &chr_nil, "number_of_non/cachable_instruction_fetches", 0x80, 0},	/* P6_IFU_IFETCH                    , "ifu_ifetch"                    , P6_IFU_FETCH                     , */
	{6, 6, "L1_inst_misses", "number_of_instruction_fetch_misses", 0x81, 0},	/* P6_IFU_IFETCH_MISS               , "ifu_ifetch_miss"               , P6_IFU_FETCH_MISS                , */
	{7, 7, "iTLB_misses", "number_of_ITLB_misses", 0x85, 0},	/* P6_ITLB_MISS                     , "itlb_miss"                     , P6_ITLB_MISS                     , */
	{8, 8, (str) &chr_nil, "cycles_instruction_fetch_pipe_is_stalled", 0x86, 0},	/* P6_IFU_MEM_STALL                 , "ifu_mem_stall"                 , P6_IFU_MEM_STALL                 , */
	{9, 9, (str) &chr_nil, "cycles_instruction_length_decoder_is_stalled", 0x87, 0},	/* P6_ILD_STALL                     , "ild_stall"                     , P6_ILD_STALL                     , */
	{10, 10, (str) &chr_nil, "number_of_L2_instruction_fetches", 0x28, 0xF},	/* P6_L2_IFETCH                     , "l2_ifetch"                     , P6_L2_IFETCH                     , */
	{11, 11, (str) &chr_nil, "number_of_L2_data_loads", 0x29, 0xF},	/* P6_L2_LD                         , "l2_ld"                         , P6_L2_LD                         , */
	{12, 12, (str) &chr_nil, "number_of_L2_data_stores", 0x2a, 0xF},	/* P6_L2_ST                         , "l2_st"                         , P6_L2_ST                         , */
	{13, 13, "L2_data_misses", "number_of_allocated_lines_in_L2", 0x24, 0},	/* P6_L2_LINES_IN                   , "l2_lines_in"                   , P6_L2_LINES_IN                   , */
	{14, 14, (str) &chr_nil, "number_of_recovered_lines_from_L2", 0x26, 0},	/* P6_L2_LINES_OUT                  , "l2_lines_out"                  , P6_L2_LINES_OUT                  , */
	{15, 15, (str) &chr_nil, "number_of_modified_lines_allocated_in_L2", 0x25, 0},	/* P6_L2_M_LINES_INM                , "l2_m_lines_inm"                , P6_L2_M_LINES_INM                , */
	{16, 16, (str) &chr_nil, "number_of_modified_lines_removed_from_L2", 0x27, 0},	/* P6_L2_M_LINES_OUTM               , "l2_m_lines_outm"               , P6_L2_M_LINES_OUTM               , */
	{17, 17, (str) &chr_nil, "number_of_L2_requests", 0x2e, 0xF},	/* P6_L2_RQSTS                      , "l2_rqsts"                      , P6_L2_RQSTS                      , */
	{18, 18, (str) &chr_nil, "number_of_L2_address_strobes", 0x21, 0},	/* P6_L2_ADS                        , "l2_ads"                        , P6_L2_ADS                        , */
	{19, 19, (str) &chr_nil, "number_of_cycles_data_bus_was_busy", 0x22, 0},	/* P6_L2_DBUS_BUSY                  , "l2_dbus_busy"                  , P6_L2_DBUS_BUSY                  , */
	{20, 20, (str) &chr_nil, "cycles_data_bus_was_busy_in_xfer_from_L2_to_CPU", 0x23, 0},	/* P6_L2_DMUS_BUSY_RD               , "l2_dmus_busy_rd"               , P6_L2_DBUS_BUSY_RD               , */
	{21, 21, (str) &chr_nil, "number_of_clocks_DRDY_is_asserted", 0x62, 0},	/* P6_BUS_DRDY_CLOCKS               , "bus_drdy_clocks"               , P6_BUS_DRDY_CLOCKS               , */
	{22, 22, (str) &chr_nil, "number_of_clocks_LOCK_is_asserted", 0x63, 0},	/* P6_BUS_LOCK_CLOCKS               , "bus_lock_clocks"               , P6_BUS_LOCK_CLOCKS               , */
	{23, 23, (str) &chr_nil, "number_of_outstanding_bus_requests", 0x60, 0},	/* P6_BUS_REQ_OUTSTANDING           , "bus_req_outstanding"           , P6_BUS_REQ_OUTSTANDING           , */
	{24, 24, (str) &chr_nil, "number_of_burst_read_transactions", 0x65, 0},	/* P6_BUS_TRAN_BRD                  , "bus_tran_brd"                  , P6_BUS_TRAN_BRD                  , */
	{25, 25, (str) &chr_nil, "number_of_read_for_ownership_transactions", 0x66, 0},	/* P6_BUS_TRAN_RFO                  , "bus_tran_rfo"                  , P6_BUS_TRAN_RFO                  , */
	{26, 26, (str) &chr_nil, "number_of_write_back_transactions", 0x67, 0},	/* P6_BUS_TRANS_WB                  , "bus_trans_wb"                  , P6_BUS_TRANS_WB                  , */
	{27, 27, (str) &chr_nil, "number_of_instruction_fetch_transactions", 0x68, 0},	/* P6_BUS_TRAN_IFETCH               , "bus_tran_ifetch"               , P6_BUS_TRAN_IFETCH               , */
	{28, 28, (str) &chr_nil, "number_of_invalidate_transactions", 0x69, 0},	/* P6_BUS_TRAN_INVAL                , "bus_tran_inval"                , P6_BUS_TRAN_INVAL                , */
	{29, 29, (str) &chr_nil, "number_of_partial_write_transactions", 0x6a, 0},	/* P6_BUS_TRAN_PWR                  , "bus_tran_pwr"                  , P6_BUS_TRAN_PWR                  , */
	{30, 30, (str) &chr_nil, "number_of_partial_transactions", 0x6b, 0},	/* P6_BUS_TRANS_P                   , "bus_trans_p"                   , P6_BUS_TRANS_P                   , */
	{31, 31, (str) &chr_nil, "number_of_I/O_transactions", 0x6c, 0},	/* P6_BUS_TRANS_IO                  , "bus_trans_io"                  , P6_BUS_TRANS_IO                  , */
	{32, 32, (str) &chr_nil, "number_of_deferred_transactions", 0x6d, 0},	/* P6_BUS_TRANS_DEF                 , "bus_trans_def"                 , P6_BUS_TRAN_DEF                  , */
	{33, 33, (str) &chr_nil, "number_of_burst_transactions", 0x6e, 0},	/* P6_BUS_TRAN_BURST                , "bus_tran_burst"                , P6_BUS_TRAN_BURST                , */
	{34, 34, (str) &chr_nil, "number_of_all_transactions", 0x70, 0},	/* P6_BUS_TRAN_ANY                  , "bus_tran_any"                  , P6_BUS_TRAN_ANY                  , */
	{35, 35, (str) &chr_nil, "number_of_memory_transactions", 0x6f, 0},	/* P6_BUS_TRAN_MEM                  , "bus_tran_mem"                  , P6_BUS_TRAN_MEM                  , */
	{36, 36, (str) &chr_nil, "bus_cycles_this_processor_is_receiving_data", 0x64, 0},	/* P6_BUS_DATA_RCV                  , "bus_data_rcv"                  , P6_BUS_DATA_RCV                  , */
	{37, 37, (str) &chr_nil, "bus_cycles_this_processor_is_driving_BNR_pin", 0x61, 0},	/* P6_BUS_BNR_DRV                   , "bus_bnr_drv"                   , P6_BUS_BNR_DRV                   , */
	{38, 38, (str) &chr_nil, "bus_cycles_this_processor_is_driving_HIT_pin", 0x7a, 0},	/* P6_BUS_HIT_DRV                   , "bus_hit_drv"                   , P6_BUS_HIT_DRV                   , */
	{39, 39, (str) &chr_nil, "bus_cycles_this_processor_is_driving_HITM_pin", 0x7b, 0},	/* P6_BUS_HITM_DRV                  , "bus_hitm_drv"                  , P6_BUS_HITM_DRV                  , */
	{40, 40, (str) &chr_nil, "cycles_during_bus_snoop_stall", 0x7e, 0},	/* P6_BUS_SNOOP_STALL               , "bus_snoop_stall"               , P6_BUS_SNOOP_STALL               , */
	{41, -1, (str) &chr_nil, "number_of_computational_FP_operations_retired", 0xc1, 0},	/* P6_COMP_FLOP_RET                 , "comp_flop_ret"                 , P6_FLOPS                         , */
	{42, -1, (str) &chr_nil, "number_of_computational_FP_operations_executed", 0x10, 0},	/* P6_FLOPS                         , "flops"                         , P6_FP_COMP_OPS_EXE               , */
	{-1, 43, (str) &chr_nil, "number_of_FP_execptions_handled_by_microcode", 0x11, 0},	/* P6_FP_ASSIST                     , "fp_assist"                     , P6_FP_ASSIST                     , */
	{-1, 44, (str) &chr_nil, "number_of_multiplies", 0x12, 0},	/* P6_MUL                           , "mul"                           , P6_MUL                           , */
	{-1, 45, (str) &chr_nil, "number_of_divides", 0x13, 0},	/* P6_DIV                           , "div"                           , P6_DIV                           , */
	{46, -1, (str) &chr_nil, "cycles_divider_is_busy", 0x14, 0},	/* P6_CYCLES_DIV_BUSY               , "cycles_div_busy"               , P6_CYCLES_DIV_BUSY               , */
	{47, 47, (str) &chr_nil, "number_of_store_buffer_blocks", 0x03, 0},	/* P6_LD_BLOCKS                     , "ld_blocks"                     , P6_LD_BLOCKS                     , */
	{48, 48, (str) &chr_nil, "number_of_store_buffer_drain_cycles", 0x04, 0},	/* P6_SB_DRAINS                     , "sb_drains"                     , P6_SB_DRAINS                     , */
	{49, 49, (str) &chr_nil, "number_of_misaligned_data_memory_references", 0x05, 0},	/* P6_MISALIGN_MEM_REF              , "misalign_mem_ref"              , P6_MISALIGN_MEM_REF              , */
	{50, 50, (str) &chr_nil, "number_of_instructions_retired", 0xc0, 0},	/* P6_INST_RETIRED                  , "inst_retired"                  , P6_INST_RETIRED                  , */
	{51, 51, (str) &chr_nil, "number_of_UOPs_retired", 0xc2, 0},	/* P6_UOPS_RETIRED                  , "uops_retired"                  , P6_UOPS_RETIRED                  , */
	{52, 52, (str) &chr_nil, "number_of_instructions_decoded", 0xd0, 0},	/* P6_INST_DECODER                  , "inst_decoder"                  , P6_INST_DECODED                  , */
	{53, 53, (str) &chr_nil, "number_of_hardware_interrupts_received", 0xc8, 0},	/* P6_HW_INT_RX                     , "hw_int_rx"                     , P6_HW_INT_RX                     , */
	{54, 54, (str) &chr_nil, "cycles_interrupts_are_disabled", 0xc6, 0},	/* P6_CYCLES_INT_MASKED             , "cycles_int_masked"             , P6_CYCLES_INT_MASKED             , */
	{55, 55, (str) &chr_nil, "cycles_interrupts_are_disabled_with_pending_interrupts", 0xc7, 0},	/* P6_CYCLES_INT_PENDING_AND_MASKED , "cycles_int_pending_and_masked" , P6_CYCLES_INT_PENDING_AND_MASKED , */
	{56, 56, "branches", "number_of_branch_instructions_retired", 0xc4, 0},	/* P6_BR_INST_RETIRED               , "br_inst_retired"               , P6_BR_INST_RETIRED               , */
	{57, 57, "branch_misses", "number_of_mispredicted_branches_retired", 0xc5, 0},	/* P6_BR_MISS_PRED_RETIRED          , "br_miss_pred_retired"          , P6_BR_MISS_PRED_RETIRED          , */
	{58, 58, "Tbranches", "number_of_taken_branches_retired", 0xc9, 0},	/* P6_BR_TAKEN_RETIRED              , "br_taken_retired"              , P6_BR_TAKEN_RETIRED              , */
	{59, 59, "Tbranch_misses", "number_of_taken_mispredictions_branches_retired", 0xca, 0},	/* P6_BR_MISS_PRED_TAKEN_RET        , "br_miss_pred_taken_ret"        , P6_BR_MISS_PRED_TAKEN_RET        , */
	{60, 60, (str) &chr_nil, "number_of_branch_instructions_decoded", 0xe0, 0},	/* P6_BR_INST_DECODED               , "br_inst_decoded"               , P6_BR_INST_DECODED               , */
	{61, 61, (str) &chr_nil, "number_of_branches_that_miss_the_BTB", 0xe2, 0},	/* P6_BTB_MISSES                    , "btb_misses"                    , P6_BTB_MISSES                    , */
	{62, 62, (str) &chr_nil, "number_of_bogus_branches", 0xe4, 0},	/* P6_BR_BOGUS                      , "br_bogus"                      , P6_BR_BOGUS                      , */
	{63, 63, (str) &chr_nil, "number_of_times_BACLEAR_is_asserted", 0xe6, 0},	/* P6_BACLEARS                      , "baclears"                      , P6_BACLEARS                      , */
	{64, 64, (str) &chr_nil, "cycles_during_resource_related_stalls", 0xa2, 0},	/* P6_RESOURCE_STALLS               , "resource_stalls"               , P6_RESOURCE_STALLS               , */
	{65, 65, (str) &chr_nil, "cycles_or_events_for_partial_stalls", 0xd2, 0},	/* P6_PARTIAL_RAT_STALLS            , "partial_rat_stalls"            , P6_PARTIAL_RAT_STALLS            , */
	{66, 66, (str) &chr_nil, "number_of_segment_register_loads", 0x06, 0},	/* P6_SEGMENT_REG_LOADS             , "segment_reg_loads"             , P6_SEGMENT_REG_LOADS             , */
	{67, 67, "cycles", "clocks_processor_is_not_halted", 0x79, 0},	/* P6_CPU_CLK_UNHALTED              , "cpu_clk_unhalted"              , P6_CPU_CLK_UNHALTED              , */
	{67, 67, (str) &chr_nil, (str) &chr_nil, 0x79, 0}
};

  /* K7 (i686) Athlon */

#define K7_NUMEVENTS 57
event_t K7_event[K7_NUMEVENTS + 1] = {
	{0, 0, (str) &chr_nil, "Data cache accesses", 0x40, 0},	/* K7_DATA_MEM_REFS                   , "data_mem_refs"                   ,  0 ,  2 , K7_DATA_CACHE_ACCESSES                                        , */
	{1, 1, (str) &chr_nil, "Data cache misses", 0x41, 0},	/* K7_DCU_LINES_IN                    , "dcu_lines_in"                    ,  1 ,  3 , K7_DATA_CACHE_MISSES                                          , */
	{2, 2, "L1_data_misses", "Data cache refills from L2", 0x42, 0x1F},	/* K7_L1_MISSES                       , "L1_misses"                       ,  2 ,  4 , K7_DATA_CACHE_REFILLS                                         , */
	{3, 3, "L2_data_misses", "Data cache refills from system", 0x43, 0x1F},	/* K7_L2_MISSES                       , "L2_misses"                       ,  3 ,  5 , K7_DATA_CACHE_REFILLS_FROM_SYSTEM                             , */
	{4, 4, (str) &chr_nil, "Data cache writebacks", 0x44, 0x1F},	/* K7_DCU_WRITEBACKS                  , "dcu_writebacks"                  ,  4 ,  6 , K7_DATA_CACHE_WRITEBACKS                                      , */
	{5, 5, "TLB_misses", "L1 DTLB misses and L2 DTLB hits", 0x45, 0},	/* K7_TLB1_MISSES_PROPER              , "TLB1_misses_proper"              ,  5 ,  7 , K7_L1_DTLB_MISSES_AND_L2_DTLB_HITS                            , */
	{6, 6, (str) &chr_nil, "L1 and L2 DTLB misses", 0x46, 0},	/* K7_TLB2_MISSES                     , "TLB2_misses"                     ,  6 ,  8 , K7_L1_AND_L2_DTLB_MISSES                                      , */
	{7, 7, (str) &chr_nil, "Misaligned data references", 0x47, 0},	/* K7_MISALIGN_MEM_REF                , "misalign_mem_ref"                ,  7 ,  9 , K7_MISALIGNED_DATA_REFERENCES                                 , */
	{8, 8, (str) &chr_nil, "Instruction cache fetches", 0x80, 0},	/* K7_IFU_IFETCH                      , "ifu_ifetch"                      ,  8 , 18 , K7_INSTRUCTION_CACHE_FETCHES                                  , */
	{9, 9, (str) &chr_nil, "Instruction cache misses", 0x81, 0},	/* K7_IFU_IFETCH_MISS                 , "ifu_ifetch_miss"                 ,  9 , 19 , K7_INSTRUCTION_CACHE_MISSES                                   , */
	{10, 10, "iTLB_misses", "L1 ITLB misses (and L2 ITLB hits)", 0x84, 0},	/* K7_ITLB1_MISSES_PROPER             , "ITLB1_misses_proper"             , 10 , 22 , K7_L1_ITLB_MISSES                                             , */
	{11, 11, (str) &chr_nil, "(L1 and) L2 ITLB misses", 0x85, 0},	/* K7_ITLB2_MISSES                    , "ITLB2_misses"                    , 11 , 23 , K7_L2_ITLB_MISSES                                             , */
	{12, 12, (str) &chr_nil, "Retired instructions (includes exceptions, interrupts, resyncs)", 0xC0, 0},	/* K7_INST_RETIRED                    , "inst_retired"                    , 12 , 28 , K7_RETIRED_INSTRUCTIONS                                       , */
	{13, 13, (str) &chr_nil, "Retired Ops", 0xC1, 0},	/* K7_UOPS_RETIRED                    , "uops_retired"                    , 13 , 29 , K7_RETIRED_OPS                                                , */
	{14, 14, "branches", "Retired branches (conditional, unconditional, exceptions, interrupts)", 0xC2, 0},	/* K7_BR_INST_RETIRED                 , "br_inst_retired"                 , 14 , 30 , K7_RETIRED_BRANCHES                                           , */
	{15, 15, "branch_misses", "Retired branches mispredicted", 0xC3, 0},	/* K7_BR_MISS_PRED_RETIRED            , "br_miss_pred_retired"            , 15 , 31 , K7_RETIRED_BRANCHES_MISPREDICTED                              , */
	{16, 16, "Tbranches", "Retired taken branches", 0xC4, 0},	/* K7_BR_TAKEN_RETIRED                , "br_taken_retired"                , 16 , 32 , K7_RETIRED_TAKEN_BRANCHES                                     , */
	{17, 17, "Tbranch_misses", "Retired taken branches mispredicted", 0xC5, 0},	/* K7_BR_MISS_PRED_TAKEN_RET          , "br_miss_pred_taken_ret"          , 17 , 33 , K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED                        , */
	{18, 18, (str) &chr_nil, "Retired far control transfers", 0xC6, 0},	/* K7_FAR_CTRTF_RETIRED               , "far_ctrtf_retired"               , 18 , 34 , K7_RETIRED_FAR_CONTROL_TRANSFERS                              , */
	{19, 19, (str) &chr_nil, "Retired resync branches (only non-control transfer branches counted)", 0xC7, 0},	/* K7_BR_RESYNC_RETIRED               , "br_resync_retired"               , 19 , 35 , K7_RETIRED_RESYNC_BRANCHES                                    , */
	{20, 20, (str) &chr_nil, "Interrupts masked cycles (IF=0)", 0xCD, 0},	/* K7_CYCLES_INT_MASKED               , "cycles_int_masked"               , 20 , 39 , K7_INTERRUPTS_MASKED_CYCLES                                   , */
	{21, 21, (str) &chr_nil, "Number of taken hardware interrupts", 0xCF, 0},	/* K7_HW_INT_RX                       , "hw_int_rx"                       , 21 , 41 , K7_NUMBER_OF_TAKEN_HARDWARE_INTERRUPTS                        , */
	{22, 22, (str) &chr_nil, "Segment register loads", 0x20, 0x3F},	/* K7_seg_reg_loads                   , "seg_reg_loads"                   , 22 ,  0 , K7_SEGMENT_REGISTER_LOADS                                     , */
	{23, 23, (str) &chr_nil, "Stores to active instruction stream", 0x21, 0},	/* K7_store_to_act_instr_stream       , "store_to_act_instr_stream"       , 23 ,  1 , K7_STORES_TO_ACTIVE_INSTRUCTION_STREAM                        , */
	{24, 24, (str) &chr_nil, "DRAM system requests", 0x64, 0},	/* K7_dram_sys_req                    , "dram_sys_req"                    , 24 , 10 , K7_DRAM_SYSTEM_REQUESTS                                       , */
	{25, 25, (str) &chr_nil, "System requests with the selected type", 0x65, 0x73},	/* K7_sys_req_type                    , "sys_req_type"                    , 25 , 11 , K7_SYSTEM_REQUESTS_WITH_THE_SELECTED_TYPE                     , */
	{26, 26, (str) &chr_nil, "Snoop hits", 0x73, 0x7},	/* K7_snoop_hits                      , "snoop_hits"                      , 26 , 12 , K7_SNOOP_HITS                                                 , */
	{27, 27, (str) &chr_nil, "Single bit ECC errors detected or corrected", 0x74, 0x3},	/* K7_ecc_errors                      , "ecc_errors"                      , 27 , 13 , K7_SINGLE_BIT_ECC_ERRORS_DETECTED_OR_CORRECTED                , */
	{28, 28, (str) &chr_nil, "Internal cache line invalidates", 0x75, 0xF},	/* K7_cache_line_invalid              , "cache_line_invalid"              , 28 , 14 , K7_INTERNAL_CACHE_LINE_INVALIDATES                            , */
	{29, 29, "cycles", "Cycles processor is running", 0x76, 0},	/* K7_cyc_cpu_running                 , "cyc_cpu_running"                 , 29 , 15 , K7_CYCLES_PROCESSOR_IS_RUNNING                                , */
	{30, 30, (str) &chr_nil, "L2 requests", 0x79, 0xFF},	/* K7_L2_requests                     , "L2_requests"                     , 30 , 16 , K7_L2_REQUESTS                                                , */
	{31, 31, (str) &chr_nil, "Cycles that at least one fill request waited to use the L2", 0x7A, 0},	/* K7_cyc_fill_stall                  , "cyc_fill_stall"                  , 31 , 17 , K7_CYCLES_THAT_AT_LEAST_ONE_FILL_REQUEST_WAITED_TO_USE_THE_L2 , */
	{32, 32, (str) &chr_nil, "Snoop resyncs", 0x86, 0},	/* K7_snoop_resyncs                   , "snoop_resyncs"                   , 32 , 24 , K7_SNOOP_RESYNCS                                              , */