counters.c

一个内存数据库的源代码这是服务器端还有客户端

#line 123 "/export/scratch0/monet/monet.GNU.64.64.d.14791/MonetDB5/src/modules/kernel/counters.mx"
#include "mal_config.h"
#include "counters.h"
#include "errno.h"

#ifdef WIN32
#ifndef LIBCOUNTERS
#define counters_export extern __declspec(dllimport)
#else
#define counters_export extern __declspec(dllexport)
#endif
#else
#define counters_export extern
#endif

int NumEvents = 0, NoEvent = 0;

#if defined(HWCOUNTERS)

#if defined(HW_SunOS)
#if   defined(HAVE_LIBPERFMON)	/* libperfmon (on Solaris <= 7) */
#define LIB_SunOS(a,b) a
#elif defined(HAVE_LIBCPC)	/* libcpc     (on Solaris >= 8) */
#define LIB_SunOS(a,b) b
#endif
#endif

typedef struct {
	int id0;		/* event id for counter 0 */
	int id1;		/* event id for counter 1 */
	str unified;		/* unified event name */
	str native;		/* native event name */
#if ( defined(HW_Linux) && ( defined(HW_i568) || defined(HW_i686) || defined(HW_x86_64) ) )
	int code;		/* event code */
	int mask;		/* unit mask for "fine-tuning" of some events */
#endif
#if defined(HW_SunOS)
	 LIB_SunOS(int bits;	/* event code for perfmon on Solaris <= 7 */
		   , char *spec;	/* event spec for libcpc  on Solaris >= 8 */
	    )
#endif
} event_t;

event_t NO_event[1] = { {00, 00, (str) &chr_nil, (str) &chr_nil
#if ( defined(HW_Linux) && ( defined(HW_i568) || defined(HW_i686) || defined(HW_x86_64) ) )
			 , 00, 00
#endif
#if defined(HW_SunOS)
			 , LIB_SunOS(0, NULL)
#endif
			 }
};
event_t *event = NO_event;

#if ( defined(HW_Linux) && ( defined(HW_i568) || defined(HW_i686) || defined(HW_x86_64) ) )

#if defined(HAVE_LIBPPERF)
#include <sys/utsname.h>
#include <libpperf.h>
   /* count in user mode, only */
   /* libpperf takes care of swapping bits for P6 & K7 */
#define CPL 2
#elif defined(HAVE_LIBPERFCTR)
#include <libperfctr.h>
struct perfctr_info Info;
#endif

#define X_NUMEVENTS 0
event_t *X_event = NO_event;

  /* P5 (i586) Pentium */

#if defined(HAVE_LIBPERFCTR)
	/* sub-fields in the Control and Event Select Register (CESR)
	 *  CC0, CC1: CPL Level to Monitor, possibilities are
	 *  000 = Count Nothing
	 *  001 = Count Event while CPL = 0,1,2
	 *  010 = Count Event while CPL = 3
	 *  011 = Count Event while CPL = 0,1,2,3
	 *  100 = Count Nothing
	 *  101 = Count Clocks while CPL = 0,1,2
	 *  110 = Count Clocks while CPL = 3
	 *  111 = Count Clocks while CPL = 0,1,2,3
	 *  Here we only use 000, 001, 010 and 011.
	 */
typedef union {
	unsigned int word;	/* to initialize in one assignment */
	struct p5_cesr {
		unsigned int es0:6;	/* event select counter 0 */
		unsigned int cc0:3;	/* counter control 0 (see above) */
		unsigned int pc0:1;	/* pin control bit 0
					   0=event increment, 1=event overflow */
		unsigned int re0:6;	/* reserved */
		unsigned int es1:6;	/* event select counter 1 */
		unsigned int cc1:3;	/* counter control 1 (see cc0) */
		unsigned int pc1:1;	/* pin control bit 1 */
		unsigned int re1:6;	/* reserved */
	} cesr;
} P5_cesr_t;

	/* defaults:
	 * P5_cesr.cesr.cc0 = P5_cesr.cesr.cc1 = 2; (count in user mode, only)
	 */
P5_cesr_t P5_cesr = { (2 << 6) | (2 << 22) };
#endif

#define P5_NUMEVENTS 40
event_t P5_event[P5_NUMEVENTS + 1] = {
	{0, 0, (str) &chr_nil, "data_read_hits", 0x00, 0},	/* P5_MEM_DATA_READ         , "mem_data_read"         ,  0 ,  0 , P5_DATA_READ                                   , */
	{1, 1, (str) &chr_nil, "data_write_hits", 0x01, 0},	/* P5_MEM_DATA_WRITE        , "mem_data_write"        ,  1 ,  1 , P5_DATA_WRITE                                  , */
	{2, 2, "TLB_misses", "data_TLB_misses", 0x02, 0},	/* P5_TLB_MISS              , "tlb_miss"              ,  2 ,  2 , P5_DATA_TLB_MISS                               , */
	{3, 3, (str) &chr_nil, "data_read_misses", 0x03, 0},	/* P5_MEM_DATA_RM           , "mem_data_rm"           ,  3 ,  3 , P5_DATA_READ_MISS                              , */
	{4, 4, (str) &chr_nil, "data_write_misses", 0x04, 0},	/* P5_MEM_DATA_WM           , "mem_data_wm"           ,  4 ,  4 , P5_DATA_WRITE_MISS                             , */
	{5, 5, (str) &chr_nil, "writes_(hits)_to_M/E", 0x05, 0},	/* P5_WRITE_HIT_ME          , "write_hit_me"          ,  5 ,  5 , P5_WRITE_HIT_TO_M_OR_E_STATE_LINES             , */
	{6, 6, (str) &chr_nil, "data_cache_lines_written_back", 0x06, 0},	/* P5_DATA_CACHE_WB         , "data_cache_wb"         ,  6 ,  6 , P5_DATA_CACHE_LINES_WRITTEN_BACK               , */
	{7, 7, (str) &chr_nil, "external_snoops", 0x07, 0},	/* P5_EXT_SNOOPS            , "ext_snoops"            ,  7 ,  7 , P5_EXTERNAL_SNOOPS                             , */
	{8, 8, (str) &chr_nil, "data_cache_snoop_hits", 0x08, 0},	/* P5_DATA_CACHE_SNOOP_HITS , "data_cache_snoop_hits" ,  8 ,  8 , P5_EXTERNAL_DATA_CACHE_SNOOP_HITS              , */
	{9, 9, (str) &chr_nil, "memory_accesses_in_both_pipes", 0x09, 0},	/* P5_MEM_ACCS_BOTH_PIPES   , "mem_accs_both_pipes"   ,  9 ,  9 , P5_MEMORY_ACCESSES_IN_BOTH_PIPES               , */
	{10, 10, (str) &chr_nil, "bank_conflicts", 0x0A, 0},	/* P5_BANK_CONFLICTS        , "bank_conflicts"        , 10 , 10 , P5_BANK_CONFLICTS                              , */
	{11, 11, (str) &chr_nil, "misaligned_data_memory_references", 0x0B, 0},	/* P5_MISAL_MEM_REF         , "misal_mem_ref"         , 11 , 11 , P5_MISALIGNED_DATA_MEMORY_OR_IO_REFERENCES     , */
	{12, 12, (str) &chr_nil, "code_reads", 0x0C, 0},	/* P5_CODE_READ             , "code_read"             , 12 , 12 , P5_CODE_READ                                   , */
	{13, 13, "iTLB_misses", "code_TLB_misses", 0x0D, 0},	/* P5_CODE_TLB_MISS         , "code_tlb_miss"         , 13 , 13 , P5_CODE_TLB_MISS                               , */
	{14, 14, "L1_inst_misses", "code_cache_misses", 0x0E, 0},	/* P5_CODE_CACHE_MISS       , "code_cache_miss"       , 14 , 14 , P5_CODE_CACHE_MISS                             , */
	{15, 15, (str) &chr_nil, "segment_register_loaded", 0x0F, 0},	/* P5_SEG_REG_LOAD          , "seg_reg_load"          , 15 , 15 , P5_ANY_SEGMENT_REGISTER_LOADED                 , */
	{16, 16, (str) &chr_nil, "segment_descriptor_cache_accesses", 0x10, 0},	/* P5_SEG_DESC_CACHE_ACCS   , "seg_desc_cache_accs"   , 16 , -1 , 0                                              , */
	{17, 17, (str) &chr_nil, "segment_descriptor_cache_hits", 0x11, 0},	/* P5_SEG_DESC_CACHE_HIT    , "seg_desc_cache_hit"    , 17 , -1 , 0                                              , */
	{18, 18, "branches", "branches", 0x12, 0},	/* P5_BRANCHES              , "branches"              , 18 , 16 , P5_BRANCHES                                    , */
	{19, 19, (str) &chr_nil, "BTB_hits", 0x13, 0},	/* P5_BTB_HITS              , "btb_hits"              , 19 , 17 , P5_BTB_HITS                                    , */
	{20, 20, (str) &chr_nil, "taken_branches_or_BTB_hits", 0x14, 0},	/* P5_BRANCH_OR_BTB_HIT     , "branch_or_btb_hit"     , 20 , 18 , P5_TAKEN_BRANCH_OR_BTB_HIT                     , */
	{21, 21, (str) &chr_nil, "pipeline_flushes", 0x15, 0},	/* P5_PIPELINE_FLUSH        , "pipeline_flush"        , 21 , 19 , P5_PIPELINE_FLUSHES                            , */
	{22, 22, (str) &chr_nil, "instructions_executed_in_both_pipes", 0x16, 0},	/* P5_INS_EXE_B_PIPES       , "ins_exe_b_pipes"       , 22 , 20 , P5_INSTRUCTIONS_EXECUTED                       , */
	{23, 23, (str) &chr_nil, "instructions_executed_in_V-pipe", 0x17, 0},	/* P5_INS_EXE_V_PIPE        , "ins_exe_v_pipe"        , 23 , 21 , P5_INSTRUCTIONS_EXECUTED_IN_V_PIPE             , */
	{24, 24, (str) &chr_nil, "clocks_while_bus_cycle_in_progress", 0x18, 0},	/* P5_CLKS_BUS_CYCLE        , "clks_bus_cycle"        , 24 , 22 , P5_BUS_CYCLE_DURATION                          , */
	{25, 25, (str) &chr_nil, "pipe_stalled_by_full_write_buffers", 0x19, 0},	/* P5_PIPE_STL_FWB          , "pipe_stl_fwb"          , 25 , 23 , P5_WRITE_BUFFER_FULL_STALL_DURATION            , */
	{26, 26, (str) &chr_nil, "pipe_stalled_by_waiting_for_data_reads", 0x1A, 0},	/* P5_PIPE_STL_WDR          , "pipe_stl_wdr"          , 26 , 24 , P5_WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION , */
	{27, 27, (str) &chr_nil, "pipe_stalled_by_writes_to_M/E", 0x1B, 0},	/* P5_PIPE_STL_WME          , "pipe_stl_wme"          , 27 , 25 , P5_STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE      , */
	{28, 28, (str) &chr_nil, "locked_bus_cycles", 0x1C, 0},	/* P5_LOCKED_BUS            , "locked_bus"            , 28 , 26 , P5_LOCKED_BUS_CYCLE                            , */
	{29, 29, (str) &chr_nil, "I/O_read_or_write_cycles", 0x1D, 0},	/* P5_IO_READ_WRITE         , "io_read_write"         , 29 , 27 , P5_IO_READ_OR_WRITE_CYCLE                      , */
	{30, 30, (str) &chr_nil, "non-cacheable_memory_references", 0x1E, 0},	/* P5_NON_CACHE_MEM_REF     , "non-cache_mem_ref"     , 30 , 28 , P5_NONCACHEABLE_MEMORY_READS                   , */
	{31, 31, (str) &chr_nil, "pipeline_stalled_by_AGI", 0x1F, 0},	/* P5_PIPE_STL_AGI          , "pipe_stl_agi"          , 31 , 29 , P5_PIPELINE_AGI_STALLS                         , */
	{32, 32, (str) &chr_nil, "floating-point_operations", 0x22, 0},	/* P5_FLOPS                 , "flops"                 , 32 , 30 , P5_FLOPS                                       , */
	{33, 33, (str) &chr_nil, "breakpoint_matches_on_DR0", 0x23, 0},	/* P5_BRK_DR0               , "brk_dr0"               , 33 , 31 , P5_BREAKPOINT_MATCH_ON_DR0_REGISTER            , */
	{34, 34, (str) &chr_nil, "breakpoint_matches_on_DR1", 0x24, 0},	/* P5_BRK_DR1               , "brk_dr1"               , 34 , 32 , P5_BREAKPOINT_MATCH_ON_DR1_REGISTER            , */
	{35, 35, (str) &chr_nil, "breakpoint_matches_on_DR2", 0x25, 0},	/* P5_BRK_DR2               , "brk_dr2"               , 35 , 33 , P5_BREAKPOINT_MATCH_ON_DR2_REGISTER            , */