counters.mx

一个内存数据库的源代码这是服务器端还有客户端

	{45, 45, (str) &chr_nil, "K8_IC_STACK_HIT", 0x88, 0},
	{46, 46, (str) &chr_nil, "K8_IC_STACK_OVERFLOW", 0x89, 0},
	{47, 47, (str) &chr_nil, "K8_RETIRED_NEAR_RETURNS", 0xC8, 0},
	{48, 48, (str) &chr_nil, "K8_RETIRED_RETURNS_MISPREDICT", 0xC9, 0},
	{49, 49, (str) &chr_nil, "K8_RETIRED_BRANCH_MISCOMPARE", 0xCA, 0},
	{50, 50, (str) &chr_nil, "K8_RETIRED_FPU_INSTRS", 0xCB, 0},
	{51, 51, (str) &chr_nil, "K8_RETIRED_FASTPATH_INSTRS", 0xCC, 0},
	{52, 52, (str) &chr_nil, "K8_DECODER_EMPTY", 0xD0, 0},
	{53, 53, (str) &chr_nil, "K8_DISPATCH_STALLS", 0xD1, 0},
	{54, 54, (str) &chr_nil, "K8_DISPATCH_STALL_FROM_BRANCH_ABORT", 0xD2, 0},
	{55, 55, (str) &chr_nil, "K8_DISPATCH_STALL_SERIALIZATION", 0xD3, 0},
	{56, 56, (str) &chr_nil, "K8_DISPATCH_STALL_SEG_LOAD", 0xD4, 0},
	{57, 57, (str) &chr_nil, "K8_DISPATCH_STALL_REORDER_BUFFER", 0xD5, 0},
	{58, 58, (str) &chr_nil, "K8_DISPATCH_STALL_RESERVE_STATIONS", 0xD6, 0},
	{59, 59, (str) &chr_nil, "K8_DISPATCH_STALL_FPU", 0xD7, 0},
	{60, 60, (str) &chr_nil, "K8_DISPATCH_STALL_LS", 0xD8, 0},
	{61, 61, (str) &chr_nil, "K8_DISPATCH_STALL_QUIET_WAIT", 0xD9, 0},
	{62, 62, (str) &chr_nil, "K8_DISPATCH_STALL_PENDING", 0xDA, 0},
	{63, 63, (str) &chr_nil, "K8_FPU_EXCEPTIONS", 0xDB, 0},
	{64, 64, (str) &chr_nil, "K8_DR0_BREAKPOINTS", 0xDC, 0},
	{65, 65, (str) &chr_nil, "K8_DR1_BREAKPOINTS", 0xDD, 0},
	{66, 66, (str) &chr_nil, "K8_DR2_BREAKPOINTS", 0xDE, 0},
	{67, 67, (str) &chr_nil, "K8_DR3_BREAKPOINTS", 0xDF, 0},
	{68, 68, (str) &chr_nil, "K8_MEM_PAGE_ACCESS", 0xE0, 0},
	{69, 69, (str) &chr_nil, "K8_MEM_PAGE_TBL_OVERFLOW", 0xE1, 0},
	{70, 70, (str) &chr_nil, "K8_DRAM_SLOTS_MISSED", 0xE2, 0},
	{71, 71, (str) &chr_nil, "K8_MEM_TURNAROUND", 0xE3, 0},
	{72, 72, (str) &chr_nil, "K8_MEM_BYPASS_SAT", 0xE4, 0},
	{73, 73, (str) &chr_nil, "K8_SIZED_COMMANDS", 0xEB, 0},
	{74, 74, (str) &chr_nil, "K8_PROBE_RESULT", 0xEC, 0},
	{75, 75, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS0_WIDTH", 0xF6, 0},
	{76, 76, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS1_WIDTH", 0xF7, 0},
	{77, 77, (str) &chr_nil, "K8_HYPERTRANSPORT_BUS2_WIDTH", 0xF8, 0},
	{78, 78, (str) &chr_nil, "K8_LOCKED_OP", 0x24, 0},
	{37, 37, (str) &chr_nil, (str) &chr_nil, 0x76, 0}
};

/* P4 */
#define P4_NUMEVENTS 49
event_t P4_event[P4_NUMEVENTS + 1] = {
	/* default pefctr configurations */
	{ 0, 0, (str) &chr_nil, "P4_TC_DELIVER_MODE", 0, 0 },
	{ 1, 1, (str) &chr_nil, "P4_BPU_FETCH_REQUEST", 1, 0 },
	{ 2, 2, (str) &chr_nil, "P4_ITLB_REFERENCE", 2, 0 },
	{ 3, 3, (str) &chr_nil, "P4_MEMORY_CANCEL", 3, 0 },
	{ 4, 4, (str) &chr_nil, "P4_MEMORY_COMPLETE", 4, 0 },
	{ 5, 5, (str) &chr_nil, "P4_LOAD_PORT_REPLAY", 5, 0 },
	{ 6, 6, (str) &chr_nil, "P4_STORE_PORT_REPLAY", 6, 0 },
	{ 7, 7, (str) &chr_nil, "P4_MOB_LOAD_REPLAY", 7, 0 },
	{ 8, 8, (str) &chr_nil, "P4_PAGE_WALK_TYPE", 8, 0 },
	{ 9, 9, (str) &chr_nil, "P4_BSQ_CACHE_REFERENCE", 9, 0 },
	{ 10, 10, (str) &chr_nil, "P4_IOQ_ALLOCATION", 10, 0 },
	{ 11, 11, (str) &chr_nil, "P4_IOQ_ACTIVE_ENTRIES", 11, 0 },
	{ 12, 12, (str) &chr_nil, "P4_FSB_DATA_ACTIVITY", 12, 0 },
	{ 13, 13, (str) &chr_nil, "P4_BSQ_ALLOCATION", 13, 0 },
	{ 14, 14, (str) &chr_nil, "P4_BSQ_ACTIVE_ENTRIES", 14, 0 },
	{ 15, 15, (str) &chr_nil, "P4_SSE_INPUT_ASSIST", 15, 0 },
	{ 16, 16, (str) &chr_nil, "P4_PACKED_SP_UOP", 16, 0 },
	{ 17, 17, (str) &chr_nil, "P4_PACKED_DP_UOP", 17, 0 },
	{ 18, 18, (str) &chr_nil, "P4_SCALAR_SP_UOP", 18, 0 },
	{ 19, 19, (str) &chr_nil, "P4_SCALAR_DP_UOP", 19, 0 },
	{ 20, 20, (str) &chr_nil, "P4_64BIT_MMX_UOP", 20, 0 },
	{ 21, 21, (str) &chr_nil, "P4_128BIT_MMX_UOP", 21, 0 },
	{ 22, 22, (str) &chr_nil, "P4_X87_FP_UOP", 22, 0 },
	{ 23, 23, (str) &chr_nil, "P4_X87_SIMD_MOVES_UOP", 23, 0 },
	{ 24, 24, (str) &chr_nil, "P4_TC_MISC", 24, 0 },
	{ 25, 25, (str) &chr_nil, "P4_GLOBAL_POWER_EVENTS", 25, 0 },
	{ 26, 26, (str) &chr_nil, "P4_TC_MS_XFER", 26, 0 },
	{ 27, 27, (str) &chr_nil, "P4_UOP_QUEUE_WRITES", 27, 0 },
	{ 28, 28, (str) &chr_nil, "P4_RETIRED_MISPRED_BRANCH_TYPE", 28, 0 },
	{ 29, 29, (str) &chr_nil, "P4_RETIRED_BRANCH_TYPE", 29, 0 },
	{ 30, 30, (str) &chr_nil, "P4_RESOURCE_STALL", 30, 0 },
	{ 31, 31, (str) &chr_nil, "P4_WC_BUFFER", 31, 0 },
	{ 32, 32, (str) &chr_nil, "P4_B2B_CYCLES", 32, 0 },
	{ 33, 33, (str) &chr_nil, "P4_BNR", 33, 0 },
	{ 34, 34, (str) &chr_nil, "P4_SNOOP", 34, 0 },
	{ 35, 35, (str) &chr_nil, "P4_RESPONSE", 35, 0 },
	{ 36, 36, (str) &chr_nil, "P4_FRONT_END_EVENT", 36, 0 },
	{ 37, 37, (str) &chr_nil, "P4_EXECUTION_EVENT", 37, 0 },
	{ 38, 38, (str) &chr_nil, "P4_REPLAY_EVENT", 38, 0 },
	{ 39, 39, (str) &chr_nil, "P4_INSTR_RETIRED", 39, 0 },
	{ 40, 40, (str) &chr_nil, "P4_UOPS_RETIRED", 40, 0 },
	{ 41, 41, (str) &chr_nil, "P4_UOP_TYPE", 41, 0 },
	{ 42, 42, (str) &chr_nil, "P4_BRANCH_RETIRED", 42, 0 },
	{ 43, 43, (str) &chr_nil, "P4_MISPRED_BRANCH_RETIRED", 43, 0 },
	{ 44, 44, (str) &chr_nil, "P4_X87_ASSIST", 44, 0 },
	{ 45, 45, (str) &chr_nil, "P4_MACHINE_CLEAR", 45, 0 },
	{ 46, 46, (str) &chr_nil, "P4M3_INSTR_COMPLETED", 46, 0 },
	/* customized events (inspired by pcl library code ;)
	 * (NOTE: the P4_ names are not official, but made up by me, sandor) */
	{ 47, 47, "Load/Store Instructions", "P4_LOAD_STORE", 12, 0x100 },
	{ 48, 48, "L2 Cache Miss", "P4_L2_CACHE_MISS", 8, 0x1 },
	{ 49, 49, (str) &chr_nil, (str) &chr_nil, 49, 0}
};

#if defined(HAVE_LIBPERFCTR)
static int perfctr_event_set_count( const struct perfctr_event_set * s )
{
	int cnt = 0;

	if (s->include)
		cnt = perfctr_event_set_count(s->include);
	cnt += s->nevents;
	return cnt;
}

static const struct perfctr_event * perfctr_event_set_find( const struct perfctr_event_set * s, int cnt, int nr )
{
	cnt -= s->nevents;
	if (s->include && cnt >= nr)
		return perfctr_event_set_find(s->include, cnt, nr);
	return s->events+nr;
}

enum escr_set {
	ALF_ESCR_0_1 = 0,	/* CCCR 12/13/14/15/16/17 via ESCR select 0x01 */
	BPU_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x00 */
	BSU_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x07 */
	BSU_ESCR_0,		/* CCCR 0/1 via ESCR select 0x07 */
	BSU_ESCR_1,		/* CCCR 2/3 via ESCR select 0x07 */
	CRU_ESCR_0_1,	/* CCCR 12/13/14/15/16/17 via ESCR select 0x04 */
	CRU_ESCR_2_3,	/* CCCR 12/13/14/15/16/17 via ESCR select 0x05 */
	DAC_ESCR_0_1,	/* CCCR 8/9/10/11 via ESCR select 0x05 */
	FIRM_ESCR_0_1,	/* CCCR 8/9/10/11 via ESCR select 0x01 */
	FSB_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x06 */
	FSB_ESCR_0,		/* CCCR 0/1 via ESCR select 0x06 */
	FSB_ESCR_1,		/* CCCR 2/3 via ESCR select 0x06 */
	ITLB_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x03 */
	MOB_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x02 */
	MS_ESCR_0_1,	/* CCCR 4/5/6/7 via ESCR select 0x00 */
	PMH_ESCR_0_1,	/* CCCR 0/1/2/3 via ESCR select 0x04 */
	RAT_ESCR_0_1,	/* CCCR 12/13/14/15/16/17 via ESCR select 0x02 */
	SAAT_ESCR_0_1,	/* CCCR 8/9/10/11 via ESCR select 0x02 */
	TBPU_ESCR_0_1,	/* CCCR 4/5/6/7 via ESCR select 0x02 */
	TC_ESCR_0_1,	/* CCCR 4/5/6/7 via ESCR select 0x01 */
};

int _2ESCR(int cset, int ctr /* 0/1 */) {
	(void)ctr;
	switch(cset) {
		case ALF_ESCR_0_1: return 0x01;
		case BPU_ESCR_0_1: return 0x00;
		case BSU_ESCR_0_1: return 0x07;
		case BSU_ESCR_0: return 0x07;
		case BSU_ESCR_1: return 0x07;
		case CRU_ESCR_0_1: return 0x04;
		case CRU_ESCR_2_3: return 0x05;
		case DAC_ESCR_0_1: return 0x05;
		case FIRM_ESCR_0_1: return 0x01;
		case FSB_ESCR_0_1: return 0x06; 
		case FSB_ESCR_0: return 0x06;
		case FSB_ESCR_1: return 0x06;
		case ITLB_ESCR_0_1: return 0x03;
		case MOB_ESCR_0_1: return 0x02;
		case MS_ESCR_0_1: return 0x00;
		case PMH_ESCR_0_1: return 0x04;
		case RAT_ESCR_0_1: return 0x02; 
		case SAAT_ESCR_0_1: return 0x02;
		case TBPU_ESCR_0_1: return 0x02;
		case TC_ESCR_0_1: return 0x01;
	}
	return 0;