counters.mx

一个内存数据库的源代码这是服务器端还有客户端

} event_t;

event_t NO_event[1] = { {00, 00, (str) &chr_nil, (str) &chr_nil
#if ( defined(HW_Linux) && ( defined(HW_i568) || defined(HW_i686) || defined(HW_x86_64) ) )
			 , 00, 00
#endif
#if defined(HW_SunOS)
			 , LIB_SunOS(0, NULL)
#endif
			 }
};
event_t *event = NO_event;

#if ( defined(HW_Linux) && ( defined(HW_i568) || defined(HW_i686) || defined(HW_x86_64) ) )

#if defined(HAVE_LIBPPERF)
#include <sys/utsname.h>
#include <libpperf.h>
   /* count in user mode, only */
   /* libpperf takes care of swapping bits for P6 & K7 */
#define CPL 2
#elif defined(HAVE_LIBPERFCTR)
#include <libperfctr.h>
struct perfctr_info Info;
#endif

#define X_NUMEVENTS 0
event_t *X_event = NO_event;

  /* P5 (i586) Pentium */

#if defined(HAVE_LIBPERFCTR)
	/* sub-fields in the Control and Event Select Register (CESR)
	 *  CC0, CC1: CPL Level to Monitor, possibilities are
	 *  000 = Count Nothing
	 *  001 = Count Event while CPL = 0,1,2
	 *  010 = Count Event while CPL = 3
	 *  011 = Count Event while CPL = 0,1,2,3
	 *  100 = Count Nothing
	 *  101 = Count Clocks while CPL = 0,1,2
	 *  110 = Count Clocks while CPL = 3
	 *  111 = Count Clocks while CPL = 0,1,2,3
	 *  Here we only use 000, 001, 010 and 011.
	 */
typedef union {
	unsigned int word;	/* to initialize in one assignment */
	struct p5_cesr {
		unsigned int es0:6;	/* event select counter 0 */
		unsigned int cc0:3;	/* counter control 0 (see above) */
		unsigned int pc0:1;	/* pin control bit 0
					   0=event increment, 1=event overflow */
		unsigned int re0:6;	/* reserved */
		unsigned int es1:6;	/* event select counter 1 */
		unsigned int cc1:3;	/* counter control 1 (see cc0) */
		unsigned int pc1:1;	/* pin control bit 1 */
		unsigned int re1:6;	/* reserved */
	} cesr;
} P5_cesr_t;

	/* defaults:
	 * P5_cesr.cesr.cc0 = P5_cesr.cesr.cc1 = 2; (count in user mode, only)
	 */
P5_cesr_t P5_cesr = { (2 << 6) | (2 << 22) };
#endif

#define P5_NUMEVENTS 40
event_t P5_event[P5_NUMEVENTS + 1] = {
	{0, 0, (str) &chr_nil, "data_read_hits", 0x00, 0},	/* P5_MEM_DATA_READ         , "mem_data_read"         ,  0 ,  0 , P5_DATA_READ                                   , */
	{1, 1, (str) &chr_nil, "data_write_hits", 0x01, 0},	/* P5_MEM_DATA_WRITE        , "mem_data_write"        ,  1 ,  1 , P5_DATA_WRITE                                  , */
	{2, 2, "TLB_misses", "data_TLB_misses", 0x02, 0},	/* P5_TLB_MISS              , "tlb_miss"              ,  2 ,  2 , P5_DATA_TLB_MISS                               , */
	{3, 3, (str) &chr_nil, "data_read_misses", 0x03, 0},	/* P5_MEM_DATA_RM           , "mem_data_rm"           ,  3 ,  3 , P5_DATA_READ_MISS                              , */
	{4, 4, (str) &chr_nil, "data_write_misses", 0x04, 0},	/* P5_MEM_DATA_WM           , "mem_data_wm"           ,  4 ,  4 , P5_DATA_WRITE_MISS                             , */
	{5, 5, (str) &chr_nil, "writes_(hits)_to_M/E", 0x05, 0},	/* P5_WRITE_HIT_ME          , "write_hit_me"          ,  5 ,  5 , P5_WRITE_HIT_TO_M_OR_E_STATE_LINES             , */
	{6, 6, (str) &chr_nil, "data_cache_lines_written_back", 0x06, 0},	/* P5_DATA_CACHE_WB         , "data_cache_wb"         ,  6 ,  6 , P5_DATA_CACHE_LINES_WRITTEN_BACK               , */
	{7, 7, (str) &chr_nil, "external_snoops", 0x07, 0},	/* P5_EXT_SNOOPS            , "ext_snoops"            ,  7 ,  7 , P5_EXTERNAL_SNOOPS                             , */
	{8, 8, (str) &chr_nil, "data_cache_snoop_hits", 0x08, 0},	/* P5_DATA_CACHE_SNOOP_HITS , "data_cache_snoop_hits" ,  8 ,  8 , P5_EXTERNAL_DATA_CACHE_SNOOP_HITS              , */
	{9, 9, (str) &chr_nil, "memory_accesses_in_both_pipes", 0x09, 0},	/* P5_MEM_ACCS_BOTH_PIPES   , "mem_accs_both_pipes"   ,  9 ,  9 , P5_MEMORY_ACCESSES_IN_BOTH_PIPES               , */
	{10, 10, (str) &chr_nil, "bank_conflicts", 0x0A, 0},	/* P5_BANK_CONFLICTS        , "bank_conflicts"        , 10 , 10 , P5_BANK_CONFLICTS                              , */
	{11, 11, (str) &chr_nil, "misaligned_data_memory_references", 0x0B, 0},	/* P5_MISAL_MEM_REF         , "misal_mem_ref"         , 11 , 11 , P5_MISALIGNED_DATA_MEMORY_OR_IO_REFERENCES     , */
	{12, 12, (str) &chr_nil, "code_reads", 0x0C, 0},	/* P5_CODE_READ             , "code_read"             , 12 , 12 , P5_CODE_READ                                   , */
	{13, 13, "iTLB_misses", "code_TLB_misses", 0x0D, 0},	/* P5_CODE_TLB_MISS         , "code_tlb_miss"         , 13 , 13 , P5_CODE_TLB_MISS                               , */
	{14, 14, "L1_inst_misses", "code_cache_misses", 0x0E, 0},	/* P5_CODE_CACHE_MISS       , "code_cache_miss"       , 14 , 14 , P5_CODE_CACHE_MISS                             , */
	{15, 15, (str) &chr_nil, "segment_register_loaded", 0x0F, 0},	/* P5_SEG_REG_LOAD          , "seg_reg_load"          , 15 , 15 , P5_ANY_SEGMENT_REGISTER_LOADED                 , */
	{16, 16, (str) &chr_nil, "segment_descriptor_cache_accesses", 0x10, 0},	/* P5_SEG_DESC_CACHE_ACCS   , "seg_desc_cache_accs"   , 16 , -1 , 0                                              , */
	{17, 17, (str) &chr_nil, "segment_descriptor_cache_hits", 0x11, 0},	/* P5_SEG_DESC_CACHE_HIT    , "seg_desc_cache_hit"    , 17 , -1 , 0                                              , */
	{18, 18, "branches", "branches", 0x12, 0},	/* P5_BRANCHES              , "branches"              , 18 , 16 , P5_BRANCHES                                    , */
	{19, 19, (str) &chr_nil, "BTB_hits", 0x13, 0},	/* P5_BTB_HITS              , "btb_hits"              , 19 , 17 , P5_BTB_HITS                                    , */
	{20, 20, (str) &chr_nil, "taken_branches_or_BTB_hits", 0x14, 0},	/* P5_BRANCH_OR_BTB_HIT     , "branch_or_btb_hit"     , 20 , 18 , P5_TAKEN_BRANCH_OR_BTB_HIT                     , */
	{21, 21, (str) &chr_nil, "pipeline_flushes", 0x15, 0},	/* P5_PIPELINE_FLUSH        , "pipeline_flush"        , 21 , 19 , P5_PIPELINE_FLUSHES                            , */
	{22, 22, (str) &chr_nil, "instructions_executed_in_both_pipes", 0x16, 0},	/* P5_INS_EXE_B_PIPES       , "ins_exe_b_pipes"       , 22 , 20 , P5_INSTRUCTIONS_EXECUTED                       , */
	{23, 23, (str) &chr_nil, "instructions_executed_in_V-pipe", 0x17, 0},	/* P5_INS_EXE_V_PIPE        , "ins_exe_v_pipe"        , 23 , 21 , P5_INSTRUCTIONS_EXECUTED_IN_V_PIPE             , */
	{24, 24, (str) &chr_nil, "clocks_while_bus_cycle_in_progress", 0x18, 0},	/* P5_CLKS_BUS_CYCLE        , "clks_bus_cycle"        , 24 , 22 , P5_BUS_CYCLE_DURATION                          , */
	{25, 25, (str) &chr_nil, "pipe_stalled_by_full_write_buffers", 0x19, 0},	/* P5_PIPE_STL_FWB          , "pipe_stl_fwb"          , 25 , 23 , P5_WRITE_BUFFER_FULL_STALL_DURATION            , */
	{26, 26, (str) &chr_nil, "pipe_stalled_by_waiting_for_data_reads", 0x1A, 0},	/* P5_PIPE_STL_WDR          , "pipe_stl_wdr"          , 26 , 24 , P5_WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION , */
	{27, 27, (str) &chr_nil, "pipe_stalled_by_writes_to_M/E", 0x1B, 0},	/* P5_PIPE_STL_WME          , "pipe_stl_wme"          , 27 , 25 , P5_STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE      , */
	{28, 28, (str) &chr_nil, "locked_bus_cycles", 0x1C, 0},	/* P5_LOCKED_BUS            , "locked_bus"            , 28 , 26 , P5_LOCKED_BUS_CYCLE                            , */
	{29, 29, (str) &chr_nil, "I/O_read_or_write_cycles", 0x1D, 0},	/* P5_IO_READ_WRITE         , "io_read_write"         , 29 , 27 , P5_IO_READ_OR_WRITE_CYCLE                      , */
	{30, 30, (str) &chr_nil, "non-cacheable_memory_references", 0x1E, 0},	/* P5_NON_CACHE_MEM_REF     , "non-cache_mem_ref"     , 30 , 28 , P5_NONCACHEABLE_MEMORY_READS                   , */
	{31, 31, (str) &chr_nil, "pipeline_stalled_by_AGI", 0x1F, 0},	/* P5_PIPE_STL_AGI          , "pipe_stl_agi"          , 31 , 29 , P5_PIPELINE_AGI_STALLS                         , */
	{32, 32, (str) &chr_nil, "floating-point_operations", 0x22, 0},	/* P5_FLOPS                 , "flops"                 , 32 , 30 , P5_FLOPS                                       , */
	{33, 33, (str) &chr_nil, "breakpoint_matches_on_DR0", 0x23, 0},	/* P5_BRK_DR0               , "brk_dr0"               , 33 , 31 , P5_BREAKPOINT_MATCH_ON_DR0_REGISTER            , */
	{34, 34, (str) &chr_nil, "breakpoint_matches_on_DR1", 0x24, 0},	/* P5_BRK_DR1               , "brk_dr1"               , 34 , 32 , P5_BREAKPOINT_MATCH_ON_DR1_REGISTER            , */
	{35, 35, (str) &chr_nil, "breakpoint_matches_on_DR2", 0x25, 0},	/* P5_BRK_DR2               , "brk_dr2"               , 35 , 33 , P5_BREAKPOINT_MATCH_ON_DR2_REGISTER            , */
	{36, 36, (str) &chr_nil, "breakpoint_matches_on_DR3", 0x26, 0},	/* P5_BRK_DR3               , "brk_dr3"               , 36 , 34 , P5_BREAKPOINT_MATCH_ON_DR3_REGISTER            , */
	{37, 37, (str) &chr_nil, "hardware_interrupts", 0x27, 0},	/* P5_HDW_INT               , "hdw_int"               , 37 , 35 , P5_HARDWARE_INTERRUPTS                         , */
	{38, 38, (str) &chr_nil, "data_reads_or_writes", 0x28, 0},	/* P5_MEM_READ_WRITE_HIT    , "mem_read_write_hit"    , 38 , 36 , P5_DATA_READ_OR_WRITE                          , */
	{39, 39, "L1_data_misses", "data_read/write_misses", 0x29, 0},	/* P5_MEM_READ_WRITE_MISS   , "mem_read_write_miss"   , 39 , 37 , P5_DATA_READ_MISS_OR_WRITE_MISS                , */
	{22, 22, (str) &chr_nil, (str) &chr_nil, 0x16, 0}
};

  /* P6 (i686) PentiumPro/PentiumII/PentiumIII/Celeron */

#if defined(HAVE_LIBPERFCTR)
typedef union {
	unsigned int word;	/* to initialize in one assignment */
	struct p6_k7_cesr {
		unsigned int evsel:8;	/* event select */
		unsigned int umask:8;	/* further qualifies event (MESI) */
		unsigned int usr:1;	/* count in user mode (CPL=1,2,3) */
		unsigned int os:1;	/* count in os mode (CPL=0) */
		unsigned int e:1;	/* edge detect */
		unsigned int pc:1;	/* pin control */
		unsigned int aint:1;	/* local APIC interrupt enable on overflow */
		unsigned int res:1;	/* reserved */
		unsigned int en:1;	/* enable counters (P6: sel0 only!) */
		unsigned int inv:1;	/* invert counter mask */
		unsigned int cmask:8;	/* if!0, compare with events */
	} cesr;
} P6_K7_cesr_t;

	/* defaults:
	 * P6_K7_cesr0.cesr.usr = P6_K7_cesr1.cesr.usr = 1; (count in user mode, only)
	 * P6_K7_cesr0.cesr.en  = P6_K7_cesr1.cesr.en  = 1;
	 */
P6_K7_cesr_t P6_K7_cesr0 = { ((1 << 16) | (1 << 22)) }, P6_K7_cesr1 = {
((1 << 16) | (1 << 22))};
#endif

#define P6_NUMEVENTS 68
event_t P6_event[P6_NUMEVENTS + 1] = {
	{0, 0, (str) &chr_nil, "all_memory_references,_cachable_and_non", 0x43, 0},	/* P6_DATA_MEM_REFS                 , "data_mem_refs"                 , P6_DATA_MEM_REFS                 , */
	{1, 1, "L1_data_misses", "total_lines_allocated_in_the_DCU", 0x45, 0},	/* P6_DCU_LINES_IN                  , "dcu_lines_in"                  , P6_DCU_LINES_IN                  , */
	{2, 2, (str) &chr_nil, "number_of_M_state_lines_allocated_in_DCU", 0x46, 0},	/* P6_DCU_M_LINES_IN                , "dcu_m_lines_in"                , P6_DCU_M_LINES_IN                , */
	{3, 3, (str) &chr_nil, "number_of_M_lines_evicted_from_the_DCU", 0x47, 0},	/* P6_DCU_M_LINES_OUT               , "dcu_m_lines_out"               , P6_DCU_M_LINES_OUT               , */
	{4, 4, (str) &chr_nil, "number_of_cycles_while_DCU_miss_outstanding", 0x48, 0},	/* P6_DCU_MISS_OUTSTANDING          , "dcu_miss_outstanding"          , P6_DCU_MISS_OUTSTANDING          , */
	{5, 5, (str) &chr_nil, "number_of_non/cachable_instruction_fetches", 0x80, 0},	/* P6_IFU_IFETCH                    , "ifu_ifetch"                    , P6_IFU_FETCH                     , */
	{6, 6, "L1_inst_misses", "number_of_instruction_fetch_misses", 0x81, 0},	/* P6_IFU_IFETCH_MISS               , "ifu_ifetch_miss"               , P6_IFU_FETCH_MISS                , */
	{7, 7, "iTLB_misses", "number_of_ITLB_misses", 0x85, 0},	/* P6_ITLB_MISS                     , "itlb_miss"                     , P6_ITLB_MISS                     , */
	{8, 8, (str) &chr_nil, "cycles_instruction_fetch_pipe_is_stalled", 0x86, 0},	/* P6_IFU_MEM_STALL                 , "ifu_mem_stall"                 , P6_IFU_MEM_STALL                 , */
	{9, 9, (str) &chr_nil, "cycles_instruction_length_decoder_is_stalled", 0x87, 0},	/* P6_ILD_STALL                     , "ild_stall"                     , P6_ILD_STALL                     , */
	{10, 10, (str) &chr_nil, "number_of_L2_instruction_fetches", 0x28, 0xF},	/* P6_L2_IFETCH                     , "l2_ifetch"                     , P6_L2_IFETCH                     , */
	{11, 11, (str) &chr_nil, "number_of_L2_data_loads", 0x29, 0xF},	/* P6_L2_LD                         , "l2_ld"                         , P6_L2_LD                         , */
	{12, 12, (str) &chr_nil, "number_of_L2_data_stores", 0x2a, 0xF},	/* P6_L2_ST                         , "l2_st"                         , P6_L2_ST                         , */
	{13, 13, "L2_data_misses", "number_of_allocated_lines_in_L2", 0x24, 0},	/* P6_L2_LINES_IN                   , "l2_lines_in"                   , P6_L2_LINES_IN                   , */
	{14, 14, (str) &chr_nil, "number_of_recovered_lines_from_L2", 0x26, 0},	/* P6_L2_LINES_OUT                  , "l2_lines_out"                  , P6_L2_LINES_OUT                  , */
	{15, 15, (str) &chr_nil, "number_of_modified_lines_allocated_in_L2", 0x25, 0},	/* P6_L2_M_LINES_INM                , "l2_m_lines_inm"                , P6_L2_M_LINES_INM                , */
	{16, 16, (str) &chr_nil, "number_of_modified_lines_removed_from_L2", 0x27, 0},	/* P6_L2_M_LINES_OUTM               , "l2_m_lines_outm"               , P6_L2_M_LINES_OUTM               , */
	{17, 17, (str) &chr_nil, "number_of_L2_requests", 0x2e, 0xF},	/* P6_L2_RQSTS                      , "l2_rqsts"                      , P6_L2_RQSTS                      , */
	{18, 18, (str) &chr_nil, "number_of_L2_address_strobes", 0x21, 0},	/* P6_L2_ADS                        , "l2_ads"                        , P6_L2_ADS                        , */
	{19, 19, (str) &chr_nil, "number_of_cycles_data_bus_was_busy", 0x22, 0},	/* P6_L2_DBUS_BUSY                  , "l2_dbus_busy"                  , P6_L2_DBUS_BUSY                  , */
	{20, 20, (str) &chr_nil, "cycles_data_bus_was_busy_in_xfer_from_L2_to_CPU", 0x23, 0},	/* P6_L2_DMUS_BUSY_RD               , "l2_dmus_busy_rd"               , P6_L2_DBUS_BUSY_RD               , */
	{21, 21, (str) &chr_nil, "number_of_clocks_DRDY_is_asserted", 0x62, 0},	/* P6_BUS_DRDY_CLOCKS               , "bus_drdy_clocks"               , P6_BUS_DRDY_CLOCKS               , */