📄 ativga.c
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c,v 1.20 2003/04/23 21:51:31 tsi Exp $ *//* $XdotOrg: xc/programs/Xserver/hw/xfree86/drivers/ati/ativga.c,v 1.4 2005/06/04 20:26:28 alanc Exp $ *//* * Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that * the above copyright notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting documentation, and * that the name of Marc Aurele La France not be used in advertising or * publicity pertaining to distribution of the software without specific, * written prior permission. Marc Aurele La France makes no representations * about the suitability of this software for any purpose. It is provided * "as-is" without express or implied warranty. * * MARC AURELE LA FRANCE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO * EVENT SHALL MARC AURELE LA FRANCE BE LIABLE FOR ANY SPECIAL, INDIRECT OR * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */#ifdef HAVE_CONFIG_H#include "config.h"#endif#include "ati.h"#include "atiadapter.h"#include "atichip.h"#include "atimono.h"#include "atistruct.h"#include "ativga.h"#include "ativgaio.h"#ifndef DPMS_SERVER# define DPMS_SERVER#endif#include <X11/extensions/dpms.h>#ifndef AVOID_CPIO/* * ATIVGAPreInit -- * * This function is called to set up VGA-related data that is common to all * video modes generated by the driver. */voidATIVGAPreInit( ATIPtr pATI, ATIHWPtr pATIHW){ int Index; /* Initialise sequencer register values */ pATIHW->seq[0] = 0x03U; if (pATI->depth == 1) pATIHW->seq[2] = 0x01U << BIT_PLANE; else pATIHW->seq[2] = 0x0FU; if (pATI->depth <= 4) pATIHW->seq[4] = 0x06U; else if (pATI->Adapter == ATI_ADAPTER_VGA) pATIHW->seq[4] = 0x0EU; else pATIHW->seq[4] = 0x0AU; /* Initialise CRTC register values */ if ((pATI->depth >= 8) && ((pATI->Chip >= ATI_CHIP_264CT) || (pATI->CPIO_VGAWonder && (pATI->Chip <= ATI_CHIP_18800_1) && (pATI->VideoRAM == 256)))) pATIHW->crt[19] = pATI->displayWidth >> 3; else pATIHW->crt[19] = pATI->displayWidth >> 4; if ((pATI->depth >= 8) && (pATI->Adapter == ATI_ADAPTER_VGA)) pATIHW->crt[23] = 0xC3U; else pATIHW->crt[23] = 0xE3U; pATIHW->crt[24] = 0xFFU; /* Initialise attribute controller register values */ if (pATI->depth == 1) { Bool FlipPixels = xf86GetFlipPixels(); for (Index = 0; Index < 16; Index++) if (((Index & (0x01U << BIT_PLANE)) != 0) != FlipPixels) pATIHW->attr[Index] = MONO_WHITE; else pATIHW->attr[Index] = MONO_BLACK; pATIHW->attr[16] = 0x01U; pATIHW->attr[17] = MONO_OVERSCAN; } else { for (Index = 0; Index < 16; Index++) pATIHW->attr[Index] = Index; if (pATI->depth <= 4) pATIHW->attr[16] = 0x81U; else if (pATI->Adapter == ATI_ADAPTER_VGA) pATIHW->attr[16] = 0x41U; else pATIHW->attr[16] = 0x01U; pATIHW->attr[17] = 0xFFU; } pATIHW->attr[18] = 0x0FU; /* Initialise graphics controller register values */ if (pATI->depth == 1) pATIHW->gra[4] = BIT_PLANE; else if (pATI->depth <= 4) pATIHW->gra[5] = 0x02U; else if (pATI->Chip >= ATI_CHIP_264CT) pATIHW->gra[5] = 0x40U; if (pATI->UseSmallApertures && (pATI->Chip >= ATI_CHIP_264CT) && ((pATI->Chip >= ATI_CHIP_264VT) || !pATI->LinearBase)) pATIHW->gra[6] = 0x01U; /* 128kB aperture */ else pATIHW->gra[6] = 0x05U; /* 64kB aperture */ pATIHW->gra[7] = 0x0FU; pATIHW->gra[8] = 0xFFU;}/* * ATIVGASave -- * * This function is called to save the VGA portion of the current video state. */voidATIVGASave( ATIPtr pATI, ATIHWPtr pATIHW){ int Index; /* Save miscellaneous output register */ pATIHW->genmo = inb(R_GENMO); ATISetVGAIOBase(pATI, pATIHW->genmo); /* Save sequencer registers */ for (Index = 0; Index < NumberOf(pATIHW->seq); Index++) pATIHW->seq[Index] = GetReg(SEQX, Index); /* Save CRTC registers */ for (Index = 0; Index < NumberOf(pATIHW->crt); Index++) pATIHW->crt[Index] = GetReg(CRTX(pATI->CPIO_VGABase), Index); /* Save attribute controller registers */ for (Index = 0; Index < NumberOf(pATIHW->attr); Index++) { (void)inb(GENS1(pATI->CPIO_VGABase)); /* Reset flip-flop */ pATIHW->attr[Index] = GetReg(ATTRX, Index); } /* Save graphics controller registers */ for (Index = 0; Index < NumberOf(pATIHW->gra); Index++) pATIHW->gra[Index] = GetReg(GRAX, Index);}/* * ATIVGACalculate -- * * This function fills in the VGA portion of an ATIHWRec. */voidATIVGACalculate( ATIPtr pATI, ATIHWPtr pATIHW, DisplayModePtr pMode){ int Index, VDisplay; /* If not already done, adjust horizontal timings */ if (!pMode->CrtcHAdjusted) { pMode->CrtcHAdjusted = TRUE; pMode->CrtcHDisplay = (pMode->HDisplay >> 3) - 1; pMode->CrtcHBlankStart = (pMode->HDisplay >> 3); if ((pATI->Chip == ATI_CHIP_18800_1) || (pATI->Chip >= ATI_CHIP_264CT)) pMode->CrtcHBlankStart--; pMode->CrtcHSyncStart = pMode->HSyncStart >> 3; if (pATI->LCDPanelID >= 0) pMode->CrtcHSyncStart--; pMode->CrtcHSyncEnd = pMode->HSyncEnd >> 3; if (pATI->LCDPanelID >= 0) pMode->CrtcHSyncEnd--; pMode->CrtcHBlankEnd = (pMode->HTotal >> 3) - 1; pMode->CrtcHTotal = (pMode->HTotal >> 3) - 5; pMode->CrtcHSkew = pMode->HSkew; /* Check sync pulse width */ Index = pMode->CrtcHSyncEnd - pMode->CrtcHSyncStart - 0x1F; if (Index > 0) { pMode->CrtcHSyncStart += Index / 2; pMode->CrtcHSyncEnd = pMode->CrtcHSyncStart + 0x1F; } /* Check blank pulse width */ Index = pMode->CrtcHBlankEnd - pMode->CrtcHBlankStart - 0x3F; if (Index > 0) { if ((pMode->CrtcHBlankEnd - Index) > pMode->CrtcHSyncEnd) { pMode->CrtcHBlankStart += Index / 2; if (pMode->CrtcHBlankStart >= pMode->CrtcHSyncStart) pMode->CrtcHBlankStart = pMode->CrtcHSyncStart - 1; pMode->CrtcHBlankEnd = pMode->CrtcHBlankStart + 0x3F; } else { Index -= 0x40; if (Index > 0) { pMode->CrtcHBlankStart += Index / 2; if (pMode->CrtcHBlankStart >= pMode->CrtcHSyncStart) pMode->CrtcHBlankStart = pMode->CrtcHSyncStart - 1; pMode->CrtcHBlankEnd = pMode->CrtcHBlankStart + 0x7F; } } } } /* * Because of the use of CRTC[23] bit 0x04's for vertical doubling, it is * necessary to always re-adjust vertical timings here. */ pMode->CrtcVDisplay = pMode->VDisplay; pMode->CrtcVBlankStart = pMode->VDisplay; pMode->CrtcVSyncStart = pMode->VSyncStart; pMode->CrtcVSyncEnd = pMode->VSyncEnd; pMode->CrtcVBlankEnd = pMode->VTotal; pMode->CrtcVTotal = pMode->VTotal; /* Adjust for doublescanned modes */ if (pMode->Flags & V_DBLSCAN) { pMode->CrtcVDisplay <<= 1; pMode->CrtcVBlankStart <<= 1; pMode->CrtcVSyncStart <<= 1; pMode->CrtcVSyncEnd <<= 1; pMode->CrtcVBlankEnd <<= 1; pMode->CrtcVTotal <<= 1; } /* Adjust for multiscanned modes */ if (pMode->VScan > 1) { pMode->CrtcVDisplay *= pMode->VScan; pMode->CrtcVBlankStart *= pMode->VScan; pMode->CrtcVSyncStart *= pMode->VScan; pMode->CrtcVSyncEnd *= pMode->VScan; pMode->CrtcVBlankEnd *= pMode->VScan; pMode->CrtcVTotal *= pMode->VScan; } /* Set up miscellaneous output register value */ pATIHW->genmo = 0x23U; if ((pMode->Flags & (V_PHSYNC | V_NHSYNC)) && (pMode->Flags & (V_PVSYNC | V_NVSYNC))) { if (pMode->Flags & V_NHSYNC) pATIHW->genmo |= 0x40U; if (pMode->Flags & V_NVSYNC)
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