atimach64.c

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        /* Load source registers */
        ATIMach64WaitForFIFO(pATI, 6);
        outf(SRC_OFF_PITCH, pATIHW->src_off_pitch);
        outf(SRC_Y_X, SetWord(pATIHW->src_x, 1) | SetWord(pATIHW->src_y, 0));
        outf(SRC_HEIGHT1_WIDTH1,
            SetWord(pATIHW->src_width1, 1) | SetWord(pATIHW->src_height1, 0));
        outf(SRC_Y_X_START,
            SetWord(pATIHW->src_x_start, 1) | SetWord(pATIHW->src_y_start, 0));
        outf(SRC_HEIGHT2_WIDTH2,
            SetWord(pATIHW->src_width2, 1) | SetWord(pATIHW->src_height2, 0));
        outf(SRC_CNTL, pATIHW->src_cntl);

        if (pATI->Chip >= ATI_CHIP_264GTPRO)
        {
            CARD32 offset = TEX_LEVEL(pATIHW->tex_size_pitch);

            /* Load 3D control & texture registers */
            ATIMach64WaitForFIFO(pATI, 2);
            outf(TEX_0_OFF + offset, pATIHW->tex_offset);
            outf(SCALE_3D_CNTL, pATIHW->scale_3d_cntl);
        }

        /* Load host data register */
        ATIMach64WaitForFIFO(pATI, 1);
        outf(HOST_CNTL, pATIHW->host_cntl);

        /* Set host transfer window address and size clamp */
        pATI->pHOST_DATA = ATIHostDataAddr(HOST_DATA_0);
        pATI->nHostFIFOEntries = pATI->nFIFOEntries >> 1;
        if (pATI->nHostFIFOEntries > 16)
            pATI->nHostFIFOEntries = 16;

        /* Load pattern registers */
        ATIMach64WaitForFIFO(pATI, 3);
        outf(PAT_REG0, pATIHW->pat_reg0);
        outf(PAT_REG1, pATIHW->pat_reg1);
        outf(PAT_CNTL, pATIHW->pat_cntl);

        /* Load scissor registers */
        ATIMach64WaitForFIFO(pATI, 2);
        outf(SC_LEFT_RIGHT,
            SetWord(pATIHW->sc_right, 1) | SetWord(pATIHW->sc_left, 0));
        outf(SC_TOP_BOTTOM,
            SetWord(pATIHW->sc_bottom, 1) | SetWord(pATIHW->sc_top, 0));
        pATI->sc_left = pATIHW->sc_left;
        pATI->sc_right = pATIHW->sc_right;
        pATI->sc_top = pATIHW->sc_top;
        pATI->sc_bottom = pATIHW->sc_bottom;

        /* Load data path registers */
        ATIMach64WaitForFIFO(pATI, 7);
        outf(DP_BKGD_CLR, pATIHW->dp_bkgd_clr);
        outf(DP_FRGD_CLR, pATIHW->dp_frgd_clr);
        outf(DP_WRITE_MASK, pATIHW->dp_write_mask);
        outf(DP_CHAIN_MASK, pATIHW->dp_chain_mask);
        outf(DP_PIX_WIDTH, pATIHW->dp_pix_width);
        outf(DP_MIX, pATIHW->dp_mix);
        outf(DP_SRC, pATIHW->dp_src);

        /* Load colour compare registers */
        ATIMach64WaitForFIFO(pATI, 3);
        outf(CLR_CMP_CLR, pATIHW->clr_cmp_clr);
        outf(CLR_CMP_MSK, pATIHW->clr_cmp_msk);
        outf(CLR_CMP_CNTL, pATIHW->clr_cmp_cntl);

        /* Load context mask */
        ATIMach64WaitForFIFO(pATI, 1);
        outf(CONTEXT_MASK, pATIHW->context_mask);

        if (pATI->Chip >= ATI_CHIP_264GTPRO)
        {
            /* Load texture setup registers */
            ATIMach64WaitForFIFO(pATI, 2);
            outf(TEX_SIZE_PITCH, pATIHW->tex_size_pitch);
            outf(TEX_CNTL, pATIHW->tex_cntl);
        }

        if (pATI->Block1Base)
        {
            /* Load overlay & scaler registers */
            ATIMach64WaitForFIFO(pATI, 10);
            outf(OVERLAY_Y_X_START, pATIHW->overlay_y_x_start);
            outf(OVERLAY_Y_X_END, pATIHW->overlay_y_x_end);

            outf(OVERLAY_GRAPHICS_KEY_CLR, pATIHW->overlay_graphics_key_clr);
            outf(OVERLAY_GRAPHICS_KEY_MSK, pATIHW->overlay_graphics_key_msk);

            outf(OVERLAY_KEY_CNTL, pATIHW->overlay_key_cntl);

            outf(OVERLAY_SCALE_INC, pATIHW->overlay_scale_inc);
            outf(OVERLAY_SCALE_CNTL, pATIHW->overlay_scale_cntl);

            outf(SCALER_HEIGHT_WIDTH, pATIHW->scaler_height_width);

            outf(SCALER_TEST, pATIHW->scaler_test);

            outf(VIDEO_FORMAT, pATIHW->video_format);

            if (pATI->Chip < ATI_CHIP_264VTB)
            {
                ATIMach64WaitForFIFO(pATI, 4);
                outf(BUF0_OFFSET, pATIHW->buf0_offset);
                outf(BUF0_PITCH, pATIHW->buf0_pitch);
                outf(BUF1_OFFSET, pATIHW->buf1_offset);
                outf(BUF1_PITCH, pATIHW->buf1_pitch);
            }
            else
            {
                ATIMach64WaitForFIFO(pATI, 5);
                outf(SCALER_BUF0_OFFSET, pATIHW->scaler_buf0_offset);
                outf(SCALER_BUF1_OFFSET, pATIHW->scaler_buf1_offset);
                outf(SCALER_BUF_PITCH, pATIHW->scaler_buf_pitch);

                outf(OVERLAY_EXCLUSIVE_HORZ, pATIHW->overlay_exclusive_horz);
                outf(OVERLAY_EXCLUSIVE_VERT, pATIHW->overlay_exclusive_vert);

                if (pATI->Chip >= ATI_CHIP_264GTPRO)
                {
                    ATIMach64WaitForFIFO(pATI, 10);
                    outf(SCALER_COLOUR_CNTL, pATIHW->scaler_colour_cntl);

                    outf(SCALER_H_COEFF0, pATIHW->scaler_h_coeff0);
                    outf(SCALER_H_COEFF1, pATIHW->scaler_h_coeff1);
                    outf(SCALER_H_COEFF2, pATIHW->scaler_h_coeff2);
                    outf(SCALER_H_COEFF3, pATIHW->scaler_h_coeff3);
                    outf(SCALER_H_COEFF4, pATIHW->scaler_h_coeff4);

                    outf(SCALER_BUF0_OFFSET_U, pATIHW->scaler_buf0_offset_u);
                    outf(SCALER_BUF0_OFFSET_V, pATIHW->scaler_buf0_offset_v);
                    outf(SCALER_BUF1_OFFSET_U, pATIHW->scaler_buf1_offset_u);
                    outf(SCALER_BUF1_OFFSET_V, pATIHW->scaler_buf1_offset_v);
                }
            }
        }

        ATIMach64WaitForIdle(pATI);

        if (pATI->OptionMMIOCache)
        {
            /*
             * Enable write caching for selected MMIO registers.  This can only
             * be done for those registers whose value does not change without
             * driver intervention.
             */

            CacheRegister(SRC_CNTL);

            if (pATI->Chip >= ATI_CHIP_264GTPRO)
            {
                CacheRegister(SCALE_3D_CNTL);
            }

            CacheRegister(HOST_CNTL);

            CacheRegister(PAT_REG0);
            CacheRegister(PAT_REG1);
            CacheRegister(PAT_CNTL);

            CacheRegister(SC_LEFT_RIGHT);
            CacheRegister(SC_TOP_BOTTOM);

            CacheRegister(DP_BKGD_CLR);
            CacheRegister(DP_FRGD_CLR);
            CacheRegister(DP_PIX_WIDTH);
            CacheRegister(DP_MIX);

            CacheRegister(CLR_CMP_CLR);
            CacheRegister(CLR_CMP_MSK);
            CacheRegister(CLR_CMP_CNTL);

            if (pATI->Chip >= ATI_CHIP_264GTPRO)
            {
                CacheRegister(TEX_SIZE_PITCH);
            }

            if (pATI->Block1Base)
            {
                CacheRegister(OVERLAY_Y_X_START);
                CacheRegister(OVERLAY_Y_X_END);

                CacheRegister(OVERLAY_GRAPHICS_KEY_CLR);
                CacheRegister(OVERLAY_GRAPHICS_KEY_MSK);

                CacheRegister(OVERLAY_KEY_CNTL);

                CacheRegister(OVERLAY_SCALE_INC);
                CacheRegister(OVERLAY_SCALE_CNTL);

                CacheRegister(SCALER_HEIGHT_WIDTH);

                CacheRegister(SCALER_TEST);

                CacheRegister(VIDEO_FORMAT);

                if (pATI->Chip < ATI_CHIP_264VTB)
                {
                    CacheRegister(BUF0_OFFSET);
                    CacheRegister(BUF0_PITCH);
                    CacheRegister(BUF1_OFFSET);
                    CacheRegister(BUF1_PITCH);
                }
                else
                {
                    CacheRegister(SCALER_BUF0_OFFSET);
                    CacheRegister(SCALER_BUF1_OFFSET);
                    CacheRegister(SCALER_BUF_PITCH);

                    CacheRegister(OVERLAY_EXCLUSIVE_HORZ);
                    CacheRegister(OVERLAY_EXCLUSIVE_VERT);

                    if (pATI->Chip >= ATI_CHIP_264GTPRO)
                    {
                        CacheRegister(SCALER_COLOUR_CNTL);

                        CacheRegister(SCALER_H_COEFF0);
                        CacheRegister(SCALER_H_COEFF1);
                        CacheRegister(SCALER_H_COEFF2);
                        CacheRegister(SCALER_H_COEFF3);
                        CacheRegister(SCALER_H_COEFF4);

                        CacheRegister(SCALER_BUF0_OFFSET_U);
                        CacheRegister(SCALER_BUF0_OFFSET_V);
                        CacheRegister(SCALER_BUF1_OFFSET_U);
                        CacheRegister(SCALER_BUF1_OFFSET_V);
                    }
                }
            }
        }
    }

#ifndef AVOID_CPIO

    if (pATIHW->crtc == ATI_CRTC_MACH64)

#endif /* AVOID_CPIO */

    {
        /* Aperture setup */
        outr(MEM_VGA_WP_SEL, pATIHW->mem_vga_wp_sel);
        outr(MEM_VGA_RP_SEL, pATIHW->mem_vga_rp_sel);

        outr(DAC_CNTL, pATIHW->dac_cntl);

        outr(CONFIG_CNTL, pATIHW->config_cntl);
        outr(BUS_CNTL, pATIHW->bus_cntl);

        if (pATI->Chip >= ATI_CHIP_264VTB)
        {
            outr(MEM_BUF_CNTL, pATIHW->mem_buf_cntl);
            outr(MEM_CNTL, pATIHW->mem_cntl);
            outr(MPP_CONFIG, pATIHW->mpp_config);
            outr(MPP_STROBE_SEQ, pATIHW->mpp_strobe_seq);
            outr(TVO_CNTL, pATIHW->tvo_cntl);
        }
    }
}

/*
 * ATIMach64SaveScreen --
 *
 * This function blanks or unblanks a Mach64 screen.
 */
void
ATIMach64SaveScreen
(
    ATIPtr pATI,
    int    Mode
)
{
    CARD32 crtc_gen_cntl = inr(CRTC_GEN_CNTL);

    switch (Mode)
    {
        case SCREEN_SAVER_OFF:
        case SCREEN_SAVER_FORCER:
            outr(CRTC_GEN_CNTL, crtc_gen_cntl & ~CRTC_DISPLAY_DIS);
            break;

        case SCREEN_SAVER_ON:
        case SCREEN_SAVER_CYCLE:
            outr(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_DISPLAY_DIS);
            break;

        default:
            break;
    }
}

/*
 * ATIMach64SetDPMSMode --
 *
 * This function sets a Mach64's VESA Display Power Management Signaling mode.
 */
void
ATIMach64SetDPMSMode
(
    ScrnInfoPtr pScreenInfo,
    ATIPtr      pATI,
    int         DPMSMode
)
{
    CARD32 crtc_gen_cntl =
        inr(CRTC_GEN_CNTL) & ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS);

    switch (DPMSMode)
    {
        case DPMSModeOn:        /* HSync on, VSync on */
            break;

        case DPMSModeStandby:   /* HSync off, VSync on */
            crtc_gen_cntl |= CRTC_HSYNC_DIS;
            break;

        case DPMSModeSuspend:   /* HSync on, VSync off */
            crtc_gen_cntl |= CRTC_VSYNC_DIS;
            break;

        case DPMSModeOff:       /* HSync off, VSync off */
            crtc_gen_cntl |= CRTC_HSYNC_DIS | CRTC_VSYNC_DIS;
            break;

        default:                /* Muffle compiler */
            return;
    }

#ifdef XF86DRI_DEVEL

    /* XAA Sync requires the DRM lock if DRI enabled */
    ATIDRILock(pScreenInfo);

#endif /* XF86DRI_DEVEL */

    ATIMach64Sync(pScreenInfo);

    outr(CRTC_GEN_CNTL, crtc_gen_cntl);

    if (pATI->OptionPanelDisplay && (pATI->LCDPanelID >= 0))
    {
        CARD32 lcd_index = 0;

        /*
         * ATI's BIOS simply turns the panel on and off, so do the same by
         * default, but keep the previous behaviour around for reference.
         */
        if (pATI->OptionDevel)
        {
            CARD32 power_management;

            if (pATI->Chip == ATI_CHIP_264LT)
            {
                power_management = inr(POWER_MANAGEMENT);
            }
            else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
                        (pATI->Chip == ATI_CHIP_264XL) ||
                        (pATI->Chip == ATI_CHIP_MOBILITY)) */
            {
                lcd_index = inr(LCD_INDEX);
                power_management = ATIMach64GetLCDReg(LCD_POWER_MANAGEMENT);
            }

            power_management &= ~(STANDBY_NOW | SUSPEND_NOW);

            switch (DPMSMode)
            {
                case DPMSModeOn:
                    break;

                case DPMSModeStandby:
                    power_management |= STANDBY_NOW;
                    break;

                case DPMSModeSuspend:
                    power_management |= SUSPEND_NOW;
                    break;

                case DPMSModeOff:
                    power_management |= STANDBY_NOW | SUSPEND_NOW;  /* ? */
                    break;

                default:        /* Muffle compiler */
                    return;
            }

            if (pATI->Chip == ATI_CHIP_264LT)
            {
                outr(POWER_MANAGEMENT, power_management);
            }
            else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
                        (pATI->Chip == ATI_CHIP_264XL) ||
                        (pATI->Chip == ATI_CHIP_MOBILITY)) */
            {
                ATIMach64PutLCDReg(LCD_POWER_MANAGEMENT, power_management);
                outr(LCD_INDEX, lcd_index);
            }
        }
        else
        {
            CARD32 lcd_gen_ctrl;

            if (pATI->Chip == ATI_CHIP_264LT)
            {
                lcd_gen_ctrl = inr(LCD_GEN_CTRL);
            }
            else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
                        (pATI->Chip == ATI_CHIP_264XL) ||
                        (pATI->Chip == ATI_CHIP_MOBILITY)) */
            {
                lcd_index = inr(LCD_INDEX);
                lcd_gen_ctrl = ATIMach64GetLCDReg(LCD_GEN_CNTL);
            }

            if (DPMSMode == DPMSModeOn)
                lcd_gen_ctrl |= LCD_ON;
            else
                lcd_gen_ctrl &= ~LCD_ON;

            if (pATI->Chip == ATI_CHIP_264LT)
                outr(LCD_GEN_CTRL, lcd_gen_ctrl);
            else /* if ((pATI->Chip == ATI_CHIP_264LTPRO) ||
                        (pATI->Chip == ATI_CHIP_264XL) ||
                        (pATI->Chip == ATI_CHIP_MOBILITY)) */
            {
                ATIMach64PutLCDReg(LCD_GEN_CNTL, lcd_gen_ctrl);
                outr(LCD_INDEX, lcd_index);
            }
        }
    }

#ifdef XF86DRI_DEVEL

    ATIDRIUnlock(pScreenInfo);

#endif /* XF86DRI_DEVEL */

}