r128_reg.h

x.org上有关ati系列显卡最新驱动

#       define  R128_EXCL_HORZ_BACK_PORCH_MASK   0x00ff0000
#       define  R128_EXCL_HORZ_EXCLUSIVE_EN      0x80000000
#define R128_OV0_EXCLUSIVE_VERT           0x040C
#       define  R128_EXCL_VERT_START_MASK        0x000003ff
#       define  R128_EXCL_VERT_END_MASK          0x03ff0000
#define R128_OV0_REG_LOAD_CNTL            0x0410
#       define  R128_REG_LD_CTL_LOCK                 0x00000001L
#       define  R128_REG_LD_CTL_VBLANK_DURING_LOCK   0x00000002L
#       define  R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
#       define  R128_REG_LD_CTL_LOCK_READBACK        0x00000008L
#define R128_OV0_SCALE_CNTL               0x0420
#       define  R128_SCALER_PIX_EXPAND           0x00000001L
#       define  R128_SCALER_Y2R_TEMP             0x00000002L
#       define  R128_SCALER_HORZ_PICK_NEAREST    0x00000003L
#       define  R128_SCALER_VERT_PICK_NEAREST    0x00000004L
#       define  R128_SCALER_SIGNED_UV            0x00000010L
#       define  R128_SCALER_GAMMA_SEL_MASK       0x00000060L
#       define  R128_SCALER_GAMMA_SEL_BRIGHT     0x00000000L
#       define  R128_SCALER_GAMMA_SEL_G22        0x00000020L
#       define  R128_SCALER_GAMMA_SEL_G18        0x00000040L
#       define  R128_SCALER_GAMMA_SEL_G14        0x00000060L
#       define  R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
#       define  R128_SCALER_SURFAC_FORMAT        0x00000f00L
#       define  R128_SCALER_SOURCE_15BPP         0x00000300L
#       define  R128_SCALER_SOURCE_16BPP         0x00000400L
#       define  R128_SCALER_SOURCE_32BPP         0x00000600L
#       define  R128_SCALER_SOURCE_YUV9          0x00000900L
#       define  R128_SCALER_SOURCE_YUV12         0x00000A00L
#       define  R128_SCALER_SOURCE_VYUY422       0x00000B00L
#       define  R128_SCALER_SOURCE_YVYU422       0x00000C00L
#       define  R128_SCALER_SMART_SWITCH         0x00008000L
#       define  R128_SCALER_BURST_PER_PLANE      0x00ff0000L
#       define  R128_SCALER_DOUBLE_BUFFER        0x01000000L
#       define  R128_SCALER_DIS_LIMIT            0x08000000L
#       define  R128_SCALER_PRG_LOAD_START       0x10000000L
#       define  R128_SCALER_INT_EMU              0x20000000L
#       define  R128_SCALER_ENABLE               0x40000000L
#       define  R128_SCALER_SOFT_RESET           0x80000000L
#define R128_OV0_V_INC                    0x0424
#define R128_OV0_P1_V_ACCUM_INIT          0x0428
#       define  R128_OV0_P1_MAX_LN_IN_PER_LN_OUT        0x00000003L
#       define  R128_OV0_P1_V_ACCUM_INIT_MASK           0x01ff8000L
#define R128_OV0_P23_V_ACCUM_INIT         0x042C
#define R128_OV0_P1_BLANK_LINES_AT_TOP    0x0430
#       define  R128_P1_BLNK_LN_AT_TOP_M1_MASK   0x00000fffL
#       define  R128_P1_ACTIVE_LINES_M1          0x0fff0000L
#define R128_OV0_P23_BLANK_LINES_AT_TOP   0x0434
#       define  R128_P23_BLNK_LN_AT_TOP_M1_MASK  0x000007ffL
#       define  R128_P23_ACTIVE_LINES_M1         0x07ff0000L
#define R128_OV0_VID_BUF0_BASE_ADRS       0x0440
#       define  R128_VIF_BUF0_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF0_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF0_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF1_BASE_ADRS       0x0444
#       define  R128_VIF_BUF1_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF1_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF1_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF2_BASE_ADRS       0x0448
#       define  R128_VIF_BUF2_PITCH_SEL          0x00000001L
#       define  R128_VIF_BUF2_TILE_ADRS          0x00000002L
#       define  R128_VIF_BUF2_BASE_ADRS_MASK     0x03fffff0L
#       define  R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define R128_OV0_VID_BUF3_BASE_ADRS       0x044C
#define R128_OV0_VID_BUF4_BASE_ADRS       0x0450
#define R128_OV0_VID_BUF5_BASE_ADRS       0x0454
#define R128_OV0_VID_BUF_PITCH0_VALUE     0x0460
#define R128_OV0_VID_BUF_PITCH1_VALUE     0x0464
#define R128_OV0_AUTO_FLIP_CNTL           0x0470
#define R128_OV0_DEINTERLACE_PATTERN      0x0474
#define R128_OV0_H_INC                    0x0480
#define R128_OV0_STEP_BY                  0x0484
#define R128_OV0_P1_H_ACCUM_INIT          0x0488
#define R128_OV0_P23_H_ACCUM_INIT         0x048C
#define R128_OV0_P1_X_START_END           0x0494
#define R128_OV0_P2_X_START_END           0x0498
#define R128_OV0_P3_X_START_END           0x049C
#define R128_OV0_FILTER_CNTL              0x04A0
#define R128_OV0_FOUR_TAP_COEF_0          0x04B0
#define R128_OV0_FOUR_TAP_COEF_1          0x04B4
#define R128_OV0_FOUR_TAP_COEF_2          0x04B8
#define R128_OV0_FOUR_TAP_COEF_3          0x04BC
#define R128_OV0_FOUR_TAP_COEF_4          0x04C0
#define R128_OV0_COLOUR_CNTL              0x04E0
#define R128_OV0_VIDEO_KEY_CLR            0x04E4
#define R128_OV0_VIDEO_KEY_MSK            0x04E8
#define R128_OV0_GRAPHICS_KEY_CLR         0x04EC
#define R128_OV0_GRAPHICS_KEY_MSK         0x04F0
#define R128_OV0_KEY_CNTL                 0x04F4
#       define  R128_VIDEO_KEY_FN_MASK           0x00000007L
#       define  R128_VIDEO_KEY_FN_FALSE          0x00000000L
#       define  R128_VIDEO_KEY_FN_TRUE           0x00000001L
#       define  R128_VIDEO_KEY_FN_EQ             0x00000004L
#       define  R128_VIDEO_KEY_FN_NE             0x00000005L
#       define  R128_GRAPHIC_KEY_FN_MASK         0x00000070L
#       define  R128_GRAPHIC_KEY_FN_FALSE        0x00000000L
#       define  R128_GRAPHIC_KEY_FN_TRUE         0x00000010L
#       define  R128_GRAPHIC_KEY_FN_EQ           0x00000040L
#       define  R128_GRAPHIC_KEY_FN_NE           0x00000050L
#       define  R128_CMP_MIX_MASK                0x00000100L
#       define  R128_CMP_MIX_OR                  0x00000000L
#       define  R128_CMP_MIX_AND                 0x00000100L
#define R128_OV0_TEST                     0x04F8


#define R128_PALETTE_DATA                 0x00b4
#define R128_PALETTE_INDEX                0x00b0
#define R128_PC_DEBUG_MODE                0x1760
#define R128_PC_GUI_CTLSTAT               0x1748
#define R128_PC_GUI_MODE                  0x1744
#       define R128_PC_IGNORE_UNIFY       (1 << 5)
#define R128_PC_MISC_CNTL                 0x0188
#define R128_PC_NGUI_CTLSTAT              0x0184
#       define R128_PC_FLUSH_GUI          (3 << 0)
#       define R128_PC_RI_GUI             (1 << 2)
#       define R128_PC_FLUSH_ALL          0x00ff
#       define R128_PC_BUSY               (1 << 31)
#define R128_PC_NGUI_MODE                 0x0180
#define R128_PCI_GART_PAGE                0x017c
#define R128_PLANE_3D_MASK_C              0x1d44
#define R128_PLL_TEST_CNTL                0x0013 /* PLL */
#define R128_PMI_CAP_ID                   0x0f5c /* PCI */
#define R128_PMI_DATA                     0x0f63 /* PCI */
#define R128_PMI_NXT_CAP_PTR              0x0f5d /* PCI */
#define R128_PMI_PMC_REG                  0x0f5e /* PCI */
#define R128_PMI_PMCSR_REG                0x0f60 /* PCI */
#define R128_PMI_REGISTER                 0x0f5c /* PCI */
#define R128_PPLL_CNTL                    0x0002 /* PLL */
#       define R128_PPLL_RESET                (1 <<  0)
#       define R128_PPLL_SLEEP                (1 <<  1)
#       define R128_PPLL_ATOMIC_UPDATE_EN     (1 << 16)
#       define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
#define R128_PPLL_DIV_0                   0x0004 /* PLL */
#define R128_PPLL_DIV_1                   0x0005 /* PLL */
#define R128_PPLL_DIV_2                   0x0006 /* PLL */
#define R128_PPLL_DIV_3                   0x0007 /* PLL */
#       define R128_PPLL_FB3_DIV_MASK     0x07ff
#       define R128_PPLL_POST3_DIV_MASK   0x00070000
#define R128_PPLL_REF_DIV                 0x0003 /* PLL */
#       define R128_PPLL_REF_DIV_MASK     0x03ff
#       define R128_PPLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */
#       define R128_PPLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */
#define R128_P2PLL_CNTL                    0x002a /* P2PLL */
#       define R128_P2PLL_RESET               (1 <<  0)
#       define R128_P2PLL_SLEEP               (1 <<  1)
#       define R128_P2PLL_ATOMIC_UPDATE_EN    (1 << 16)
#       define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
#       define R128_P2PLL_ATOMIC_UPDATE_VSYNC  (1 << 18)
#define R128_P2PLL_DIV_0                   0x002c
#       define R128_P2PLL_FB0_DIV_MASK     0x07ff
#       define R128_P2PLL_POST0_DIV_MASK   0x00070000
#define R128_P2PLL_REF_DIV                 0x002B /* PLL */
#       define R128_P2PLL_REF_DIV_MASK     0x03ff
#       define R128_P2PLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */
#       define R128_P2PLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */
#define R128_PWR_MNGMT_CNTL_STATUS        0x0f60 /* PCI */
#define R128_REG_BASE                     0x0f18 /* PCI */
#define R128_REGPROG_INF                  0x0f09 /* PCI */
#define R128_REVISION_ID                  0x0f08 /* PCI */

#define R128_SC_BOTTOM                    0x164c
#define R128_SC_BOTTOM_RIGHT              0x16f0
#define R128_SC_BOTTOM_RIGHT_C            0x1c8c
#define R128_SC_LEFT                      0x1640
#define R128_SC_RIGHT                     0x1644
#define R128_SC_TOP                       0x1648
#define R128_SC_TOP_LEFT                  0x16ec
#define R128_SC_TOP_LEFT_C                0x1c88
#define R128_SEQ8_DATA                    0x03c5 /* VGA */
#define R128_SEQ8_IDX                     0x03c4 /* VGA */
#define R128_SNAPSHOT_F_COUNT             0x0244
#define R128_SNAPSHOT_VH_COUNTS           0x0240
#define R128_SNAPSHOT_VIF_COUNT           0x024c
#define R128_SRC_OFFSET                   0x15ac
#define R128_SRC_PITCH                    0x15b0
#define R128_SRC_PITCH_OFFSET             0x1428
#define R128_SRC_SC_BOTTOM                0x165c
#define R128_SRC_SC_BOTTOM_RIGHT          0x16f4
#define R128_SRC_SC_RIGHT                 0x1654
#define R128_SRC_X                        0x1414
#define R128_SRC_X_Y                      0x1590
#define R128_SRC_Y                        0x1418
#define R128_SRC_Y_X                      0x1434
#define R128_STATUS                       0x0f06 /* PCI */
#define R128_SUBPIC_CNTL                  0x0540 /* ? */
#define R128_SUB_CLASS                    0x0f0a /* PCI */
#define R128_SURFACE_DELAY                0x0b00
#define R128_SURFACE0_INFO                0x0b0c
#define R128_SURFACE0_LOWER_BOUND         0x0b04
#define R128_SURFACE0_UPPER_BOUND         0x0b08
#define R128_SURFACE1_INFO                0x0b1c
#define R128_SURFACE1_LOWER_BOUND         0x0b14
#define R128_SURFACE1_UPPER_BOUND         0x0b18
#define R128_SURFACE2_INFO                0x0b2c
#define R128_SURFACE2_LOWER_BOUND         0x0b24
#define R128_SURFACE2_UPPER_BOUND         0x0b28
#define R128_SURFACE3_INFO                0x0b3c
#define R128_SURFACE3_LOWER_BOUND         0x0b34
#define R128_SURFACE3_UPPER_BOUND         0x0b38
#define R128_SW_SEMAPHORE                 0x013c

#define R128_TEST_DEBUG_CNTL              0x0120
#define R128_TEST_DEBUG_MUX               0x0124
#define R128_TEST_DEBUG_OUT               0x012c
#define R128_TMDS_CRC                     0x02a0
#define R128_TMDS_TRANSMITTER_CNTL        0x02a4
#       define R128_TMDS_PLLEN            (1 << 0)
#       define R128_TMDS_PLLRST           (1 << 1)
#define R128_TRAIL_BRES_DEC               0x1614
#define R128_TRAIL_BRES_ERR               0x160c
#define R128_TRAIL_BRES_INC               0x1610
#define R128_TRAIL_X                      0x1618
#define R128_TRAIL_X_SUB                  0x1620

#define R128_VCLK_ECP_CNTL                0x0008 /* PLL */
#       define R128_VCLK_SRC_SEL_MASK     0x03
#       define R128_VCLK_SRC_SEL_CPUCLK   0x00
#       define R128_VCLK_SRC_SEL_PPLLCLK  0x03
#       define R128_ECP_DIV_MASK          (3 << 8)
#define R128_V2CLK_VCLKTV_CNTL            0x002d /* PLL */
#       define R128_V2CLK_SRC_SEL_MASK    0x03
#       define R128_V2CLK_SRC_SEL_CPUCLK  0x00
#       define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03
#define R128_VENDOR_ID                    0x0f00 /* PCI */
#define R128_VGA_DDA_CONFIG               0x02e8
#define R128_VGA_DDA_ON_OFF               0x02ec
#define R128_VID_BUFFER_CONTROL           0x0900
#define R128_VIDEOMUX_CNTL                0x0190
#define R128_VIPH_CONTROL                 0x01D0 /* ? */

#define R128_WAIT_UNTIL                   0x1720

#define R128_X_MPLL_REF_FB_DIV            0x000a /* PLL */
#define R128_XCLK_CNTL                    0x000d /* PLL */
#define R128_XDLL_CNTL                    0x000c /* PLL */
#define R128_XPLL_CNTL                    0x000b /* PLL */

				/* Registers for CCE and Microcode Engine */
#define R128_PM4_MICROCODE_ADDR           0x07d4
#define R128_PM4_MICROCODE_RADDR          0x07d8
#define R128_PM4_MICROCODE_DATAH          0x07dc
#define R128_PM4_MICROCODE_DATAL          0x07e0

#define R128_PM4_BUFFER_OFFSET            0x0700
#define R128_PM4_BUFFER_CNTL              0x0704
#       define R128_PM4_NONPM4                 (0  << 28)
#       define R128_PM4_192PIO                 (1  << 28)
#       define R128_PM4_192BM                  (2  << 28)
#       define R128_PM4_128PIO_64INDBM         (3  << 28)
#       define R128_PM4_128BM_64INDBM          (4  << 28)
#       define R128_PM4_64PIO_128INDBM         (5  << 28)
#       define R128_PM4_64BM_128INDBM          (6  << 28)
#       define R128_PM4_64PIO_64VCBM_64INDBM   (7  << 28)
#       define R128_PM4_64BM_64VCBM_64INDBM    (8  << 28)
#       define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
#define R128_PM4_BUFFER_WM_CNTL           0x0708
#       define R128_WMA_SHIFT                  0