📄 radeon_reg.h
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#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824#define RADEON_DEVICE_ID 0x0f02 /* PCI */#define RADEON_DISP_MISC_CNTL 0x0d00# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)#define RADEON_DISP_MERGE_CNTL 0x0d60# define RADEON_DISP_ALPHA_MODE_MASK 0x03# define RADEON_DISP_ALPHA_MODE_KEY 0# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1# define RADEON_DISP_ALPHA_MODE_GLOBAL 2# define RADEON_DISP_RGB_OFFSET_EN (1<<8)# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)#define RADEON_DISP2_MERGE_CNTL 0x0d68# define RADEON_DISP2_RGB_OFFSET_EN (1<<8)#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98#define RADEON_DP_BRUSH_BKGD_CLR 0x1478#define RADEON_DP_BRUSH_FRGD_CLR 0x147c#define RADEON_DP_CNTL 0x16c0# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)# define RADEON_DP_DST_TILE_LINEAR (0 << 3)# define RADEON_DP_DST_TILE_MACRO (1 << 3)# define RADEON_DP_DST_TILE_MICRO (2 << 3)# define RADEON_DP_DST_TILE_BOTH (3 << 3)#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0# define RADEON_DST_Y_MAJOR (1 << 2)# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)#define RADEON_DP_DATATYPE 0x16c4# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)#define RADEON_DP_GUI_MASTER_CNTL 0x146c# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)# define RADEON_GMC_SRC_CLIPPING (1 << 2)# define RADEON_GMC_DST_CLIPPING (1 << 3)# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)# define RADEON_GMC_BRUSH_NONE (15 << 4)# define RADEON_GMC_DST_8BPP_CI (2 << 8)# define RADEON_GMC_DST_15BPP (3 << 8)# define RADEON_GMC_DST_16BPP (4 << 8)# define RADEON_GMC_DST_24BPP (5 << 8)# define RADEON_GMC_DST_32BPP (6 << 8)# define RADEON_GMC_DST_8BPP_RGB (7 << 8)# define RADEON_GMC_DST_Y8 (8 << 8)# define RADEON_GMC_DST_RGB8 (9 << 8)# define RADEON_GMC_DST_VYUY (11 << 8)# define RADEON_GMC_DST_YVYU (12 << 8)# define RADEON_GMC_DST_AYUV444 (14 << 8)# define RADEON_GMC_DST_ARGB4444 (15 << 8)# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)# define RADEON_GMC_DST_DATATYPE_SHIFT 8# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)# define RADEON_GMC_CONVERSION_TEMP (1 << 15)# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)# define RADEON_GMC_ROP3_MASK (0xff << 16)# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)# define RADEON_GMC_3D_FCN_EN (1 << 27)# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)# define RADEON_GMC_WR_MSK_DIS (1 << 30)# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)# define RADEON_ROP3_ZERO 0x00000000# define RADEON_ROP3_DSa 0x00880000# define RADEON_ROP3_SDna 0x00440000# define RADEON_ROP3_S 0x00cc0000# define RADEON_ROP3_DSna 0x00220000# define RADEON_ROP3_D 0x00aa0000# define RADEON_ROP3_DSx 0x00660000# define RADEON_ROP3_DSo 0x00ee0000# define RADEON_ROP3_DSon 0x00110000# define RADEON_ROP3_DSxn 0x00990000# define RADEON_ROP3_Dn 0x00550000# define RADEON_ROP3_SDno 0x00dd0000# define RADEON_ROP3_Sn 0x00330000# define RADEON_ROP3_DSno 0x00bb0000# define RADEON_ROP3_DSan 0x00770000# define RADEON_ROP3_ONE 0x00ff0000# define RADEON_ROP3_DPa 0x00a00000# define RADEON_ROP3_PDna 0x00500000# define RADEON_ROP3_P 0x00f00000# define RADEON_ROP3_DPna 0x000a0000# define RADEON_ROP3_D 0x00aa0000# define RADEON_ROP3_DPx 0x005a0000# define RADEON_ROP3_DPo 0x00fa0000# define RADEON_ROP3_DPon 0x00050000# define RADEON_ROP3_PDxn 0x00a50000# define RADEON_ROP3_PDno 0x00f50000# define RADEON_ROP3_Pn 0x000f0000# define RADEON_ROP3_DPno 0x00af0000# define RADEON_ROP3_DPan 0x005f0000#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84#define RADEON_DP_MIX 0x16c8#define RADEON_DP_SRC_BKGD_CLR 0x15dc#define RADEON_DP_SRC_FRGD_CLR 0x15d8#define RADEON_DP_WRITE_MASK 0x16cc#define RADEON_DST_BRES_DEC 0x1630#define RADEON_DST_BRES_ERR 0x1628#define RADEON_DST_BRES_INC 0x162c#define RADEON_DST_BRES_LNTH 0x1634#define RADEON_DST_BRES_LNTH_SUB 0x1638#define RADEON_DST_HEIGHT 0x1410#define RADEON_DST_HEIGHT_WIDTH 0x143c#define RADEON_DST_HEIGHT_WIDTH_8 0x158c#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4#define RADEON_DST_HEIGHT_Y 0x15a0#define RADEON_DST_LINE_START 0x1600#define RADEON_DST_LINE_END 0x1604#define RADEON_DST_LINE_PATCOUNT 0x1608# define RADEON_BRES_CNTL_SHIFT 8#define RADEON_DST_OFFSET 0x1404#define RADEON_DST_PITCH 0x1408#define RADEON_DST_PITCH_OFFSET 0x142c#define RADEON_DST_PITCH_OFFSET_C 0x1c80# define RADEON_PITCH_SHIFT 21# define RADEON_DST_TILE_LINEAR (0 << 30)# define RADEON_DST_TILE_MACRO (1 << 30)# define RADEON_DST_TILE_MICRO (2 << 30)# define RADEON_DST_TILE_BOTH (3 << 30)#define RADEON_DST_WIDTH 0x140c#define RADEON_DST_WIDTH_HEIGHT 0x1598#define RADEON_DST_WIDTH_X 0x1588#define RADEON_DST_WIDTH_X_INCY 0x159c#define RADEON_DST_X 0x141c#define RADEON_DST_X_SUB 0x15a4#define RADEON_DST_X_Y 0x1594#define RADEON_DST_Y 0x1420#define RADEON_DST_Y_SUB 0x15a8#define RADEON_DST_Y_X 0x1438#define RADEON_FCP_CNTL 0x0910# define RADEON_FCP0_SRC_PCICLK 0# define RADEON_FCP0_SRC_PCLK 1# define RADEON_FCP0_SRC_PCLKb 2# define RADEON_FCP0_SRC_HREF 3# define RADEON_FCP0_SRC_GND 4# define RADEON_FCP0_SRC_HREFb 5#define RADEON_FLUSH_1 0x1704#define RADEON_FLUSH_2 0x1708#define RADEON_FLUSH_3 0x170c#define RADEON_FLUSH_4 0x1710#define RADEON_FLUSH_5 0x1714#define RADEON_FLUSH_6 0x1718#define RADEON_FLUSH_7 0x171c#define RADEON_FOG_3D_TABLE_START 0x1810#define RADEON_FOG_3D_TABLE_END 0x1814#define RADEON_FOG_3D_TABLE_DENSITY 0x181c#define RADEON_FOG_TABLE_INDEX 0x1a14#define RADEON_FOG_TABLE_DATA 0x1a18#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254#define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350#define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010#define RADEON_FP_GEN_CNTL 0x0284# define RADEON_FP_FPON (1 << 0)# define RADEON_FP_BLANK_EN (1 << 1)# define RADEON_FP_TMDS_EN (1 << 2)# define RADEON_FP_PANEL_FORMAT (1 << 3)# define RADEON_FP_EN_TMDS (1 << 7)# define RADEON_FP_DETECT_SENSE (1 << 8)# define R200_FP_SOURCE_SEL_MASK (3 << 10)# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)# define R200_FP_SOURCE_SEL_RMX (2 << 10)# define R200_FP_SOURCE_SEL_TRANS (3 << 10)# define RADEON_FP_SEL_CRTC1 (0 << 13)# define RADEON_FP_SEL_CRTC2 (1 << 13)# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)# define RADEON_FP_DFP_SYNC_SEL (1 << 21)# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)# define RADEON_FP_CRT_SYNC_SEL (1 << 23)# define RADEON_FP_USE_SHADOW_EN (1 << 24)# define RADEON_FP_CRT_SYNC_ALT (1 << 26)#define RADEON_FP2_GEN_CNTL 0x0288# define RADEON_FP2_BLANK_EN (1 << 1)# define RADEON_FP2_ON (1 << 2)# define RADEON_FP2_PANEL_FORMAT (1 << 3)# define R200_FP2_SOURCE_SEL_MASK (3 << 10)# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)# define R200_FP2_SOURCE_SEL_RMX (2 << 10)# define RADEON_FP2_SRC_SEL_MASK (3 << 13)# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)# define RADEON_FP2_FP_POL (1 << 16)# define RADEON_FP2_LP_POL (1 << 17)# define RADEON_FP2_SCK_POL (1 << 18)# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)# define RADEON_FP2_PAD_FLOP_EN (1 << 22)# define RADEON_FP2_CRC_EN (1 << 23)# define RADEON_FP2_CRC_READ_EN (1 << 24)# define RADEON_FP2_DVO_EN (1 << 25)# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)#define RADEON_FP_H_SYNC_STRT_WID 0x02c4#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4#define RADEON_FP_HORZ_STRETCH 0x028c#define RADEON_FP_HORZ2_STRETCH 0x038c# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff# define RADEON_HORZ_STRETCH_RATIO_MAX 4096# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)# define RADEON_HORZ_PANEL_SHIFT 16⌨️ 快捷键说明
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