📄 radeon_reg.h
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#define RADEON_CONFIG_APER_0_BASE 0x0100#define RADEON_CONFIG_APER_1_BASE 0x0104#define RADEON_CONFIG_APER_SIZE 0x0108#define RADEON_CONFIG_BONDS 0x00e8#define RADEON_CONFIG_CNTL 0x00e0# define RADEON_CFG_ATI_REV_A11 (0 << 16)# define RADEON_CFG_ATI_REV_A12 (1 << 16)# define RADEON_CFG_ATI_REV_A13 (2 << 16)# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)#define RADEON_CONFIG_MEMSIZE 0x00f8#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114#define RADEON_CONFIG_REG_1_BASE 0x010c#define RADEON_CONFIG_REG_APER_SIZE 0x0110#define RADEON_CONFIG_XSTRAP 0x00e4#define RADEON_CONSTANT_COLOR_C 0x1d34# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff# define RADEON_CONSTANT_COLOR_ZERO 0x00000000#define RADEON_CRC_CMDFIFO_ADDR 0x0740#define RADEON_CRC_CMDFIFO_DOUT 0x0744#define RADEON_GRPH_BUFFER_CNTL 0x02f0# define RADEON_GRPH_START_REQ_MASK (0x7f)# define RADEON_GRPH_START_REQ_SHIFT 0# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)# define RADEON_GRPH_STOP_REQ_SHIFT 8# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16# define RADEON_GRPH_CRITICAL_CNTL (1<<28)# define RADEON_GRPH_BUFFER_SIZE (1<<29)# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)# define RADEON_GRPH_STOP_CNTL (1<<31)#define RADEON_GRPH2_BUFFER_CNTL 0x03f0# define RADEON_GRPH2_START_REQ_MASK (0x7f)# define RADEON_GRPH2_START_REQ_SHIFT 0# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)# define RADEON_GRPH2_STOP_REQ_SHIFT 8# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)# define RADEON_GRPH2_BUFFER_SIZE (1<<29)# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)# define RADEON_GRPH2_STOP_CNTL (1<<31)#define RADEON_CRTC_CRNT_FRAME 0x0214#define RADEON_CRTC_EXT_CNTL 0x0054# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)# define RADEON_VGA_ATI_LINEAR (1 << 3)# define RADEON_XCRT_CNT_EN (1 << 6)# define RADEON_CRTC_HSYNC_DIS (1 << 8)# define RADEON_CRTC_VSYNC_DIS (1 << 9)# define RADEON_CRTC_DISPLAY_DIS (1 << 10)# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)# define RADEON_CRTC_CRT_ON (1 << 15)#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)#define RADEON_CRTC_GEN_CNTL 0x0050# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)# define RADEON_CRTC_INTERLACE_EN (1 << 1)# define RADEON_CRTC_CSYNC_EN (1 << 4)# define RADEON_CRTC_ICON_EN (1 << 15)# define RADEON_CRTC_CUR_EN (1 << 16)# define RADEON_CRTC_CUR_MODE_MASK (7 << 17)# define RADEON_CRTC_EXT_DISP_EN (1 << 24)# define RADEON_CRTC_EN (1 << 25)# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)#define RADEON_CRTC2_GEN_CNTL 0x03f8# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)# define RADEON_CRTC2_INTERLACE_EN (1 << 1)# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)# define RADEON_CRTC2_CRT2_ON (1 << 7)# define RADEON_CRTC2_ICON_EN (1 << 15)# define RADEON_CRTC2_CUR_EN (1 << 16)# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)# define RADEON_CRTC2_DISP_DIS (1 << 23)# define RADEON_CRTC2_EN (1 << 25)# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)# define RADEON_CRTC2_CSYNC_EN (1 << 27)# define RADEON_CRTC2_HSYNC_DIS (1 << 28)# define RADEON_CRTC2_VSYNC_DIS (1 << 29)#define RADEON_CRTC_MORE_CNTL 0x27c# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)# define RADEON_CRTC_H_SYNC_WID_SHIFT 16# define RADEON_CRTC_H_SYNC_POL (1 << 23)#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16# define RADEON_CRTC2_H_SYNC_POL (1 << 23)#define RADEON_CRTC_H_TOTAL_DISP 0x0200# define RADEON_CRTC_H_TOTAL (0x03ff << 0)# define RADEON_CRTC_H_TOTAL_SHIFT 0# define RADEON_CRTC_H_DISP (0x01ff << 16)# define RADEON_CRTC_H_DISP_SHIFT 16#define RADEON_CRTC2_H_TOTAL_DISP 0x0300# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)# define RADEON_CRTC2_H_TOTAL_SHIFT 0# define RADEON_CRTC2_H_DISP (0x01ff << 16)# define RADEON_CRTC2_H_DISP_SHIFT 16#define RADEON_CRTC_OFFSET_RIGHT 0x0220#define RADEON_CRTC_OFFSET 0x0224# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)#define RADEON_CRTC2_OFFSET 0x0324# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)#define RADEON_CRTC_OFFSET_CNTL 0x0228# define RADEON_CRTC_TILE_LINE_SHIFT 0# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)# define R300_CRTC_X_Y_MODE_EN (1 << 9)# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)# define R300_CRTC_MICRO_TILE_EN (1 << 13)# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)# define R300_CRTC_MACRO_TILE_EN (1 << 15)# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)# define RADEON_CRTC_TILE_EN (1 << 15)# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)#define R300_CRTC_TILE_X0_Y0 0x0350#define R300_CRTC2_TILE_X0_Y0 0x0358#define RADEON_CRTC2_OFFSET_CNTL 0x0328# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)# define RADEON_CRTC2_TILE_EN (1 << 15)#define RADEON_CRTC_PITCH 0x022c# define RADEON_CRTC_PITCH__SHIFT 0# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16#define RADEON_CRTC2_PITCH 0x032c#define RADEON_CRTC_STATUS 0x005c# define RADEON_CRTC_VBLANK_SAVE (1 << 1)# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)#define RADEON_CRTC2_STATUS 0x03fc# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)# define RADEON_CRTC_V_SYNC_WID_SHIFT 16# define RADEON_CRTC_V_SYNC_POL (1 << 23)#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16# define RADEON_CRTC2_V_SYNC_POL (1 << 23)#define RADEON_CRTC_V_TOTAL_DISP 0x0208# define RADEON_CRTC_V_TOTAL (0x07ff << 0)# define RADEON_CRTC_V_TOTAL_SHIFT 0# define RADEON_CRTC_V_DISP (0x07ff << 16)# define RADEON_CRTC_V_DISP_SHIFT 16#define RADEON_CRTC2_V_TOTAL_DISP 0x0308# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)# define RADEON_CRTC2_V_TOTAL_SHIFT 0# define RADEON_CRTC2_V_DISP (0x07ff << 16)# define RADEON_CRTC2_V_DISP_SHIFT 16#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)#define RADEON_CRTC2_CRNT_FRAME 0x0314#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318#define RADEON_CRTC2_STATUS 0x03fc#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */#define RADEON_CUR_CLR0 0x026c#define RADEON_CUR_CLR1 0x0270#define RADEON_CUR_HORZ_VERT_OFF 0x0268#define RADEON_CUR_HORZ_VERT_POSN 0x0264#define RADEON_CUR_OFFSET 0x0260# define RADEON_CUR_LOCK (1 << 31)#define RADEON_CUR2_CLR0 0x036c#define RADEON_CUR2_CLR1 0x0370#define RADEON_CUR2_HORZ_VERT_OFF 0x0368#define RADEON_CUR2_HORZ_VERT_POSN 0x0364#define RADEON_CUR2_OFFSET 0x0360# define RADEON_CUR2_LOCK (1 << 31)#define RADEON_DAC_CNTL 0x0058# define RADEON_DAC_RANGE_CNTL (3 << 0)# define RADEON_DAC_RANGE_CNTL_MASK 0x03# define RADEON_DAC_BLANKING (1 << 2)# define RADEON_DAC_CMP_EN (1 << 3)# define RADEON_DAC_CMP_OUTPUT (1 << 7)# define RADEON_DAC_8BIT_EN (1 << 8)# define RADEON_DAC_VGA_ADR_EN (1 << 13)# define RADEON_DAC_PDWN (1 << 15)# define RADEON_DAC_MASK_ALL (0xff << 24)#define RADEON_DAC_CNTL2 0x007c# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)#define RADEON_DAC_EXT_CNTL 0x0280# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)# define RADEON_DAC_FORCE_DATA_EN (1 << 5)# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00# define RADEON_DAC_FORCE_DATA_SHIFT 8#define RADEON_DAC_MACRO_CNTL 0x0d04# define RADEON_DAC_PDWN_R (1 << 16)# define RADEON_DAC_PDWN_G (1 << 17)# define RADEON_DAC_PDWN_B (1 << 18)#define RADEON_TV_DAC_CNTL 0x088c# define RADEON_TV_DAC_STD_MASK 0x0300# define RADEON_TV_DAC_BGSLEEP (1 << 6)# define RADEON_TV_DAC_RDACPD (1 << 24)# define RADEON_TV_DAC_GDACPD (1 << 25)# define RADEON_TV_DAC_BDACPD (1 << 26)#define RADEON_DISP_HW_DEBUG 0x0d14# define RADEON_CRT2_DISP1_SEL (1 << 5)#define RADEON_DISP_OUTPUT_CNTL 0x0d64# define RADEON_DISP_DAC_SOURCE_MASK 0x03# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04#define RADEON_DAC_CRC_SIG 0x02cc#define RADEON_DAC_DATA 0x03c9 /* VGA */#define RADEON_DAC_MASK 0x03c6 /* VGA */#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */#define RADEON_DDA_CONFIG 0x02e0#define RADEON_DDA_ON_OFF 0x02e4#define RADEON_DEFAULT_OFFSET 0x16e0#define RADEON_DEFAULT_PITCH 0x16e4⌨️ 快捷键说明
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