hardware_gfd.h

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;/////////////////////////////////////////////////////////////////
;file name: asixos.s											//
;description: the kernel,dispatch								//
;modify history: 2003-1-6 9:18 prot to ARM core	
;				2003-4-1 12:16 ADD THE MACRO DEF HA_DEBUG	
;notice:2003-3-22 13:59, in cvs ka_gfd project only the LC can modify this file
;		 othe project member can ont modify the file
;/////////////////////////////////////////////////////////////////

	
	 ;define the macro 	HA_DEBUG
	GBLL	HA_DEBUG

;////////////////////////////////////////////////////////////////////
;// Rules of Registers' Use
;////////////////////////////////////////////////////////////////////
    


R_RETURN		RN		r0             ; //with some problem,depend on the compiler,the gcc cmpiler,single return value is r0



RTA			RN		r4
RTB			RN		r5
RTC			RN		r6
RLA			RN		r7
RLB			RN		r8
RLC			RN		r9
RLD			RN		r10
RVA			RN		r11
RVB			RN		r12
RVC			RN		r13


R_ALL_0_12	 	RLIST	{ r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12 }             
                                                        
	
;//******************************************************
;//*define the onchip register of GFD
;//*******************************************************

SP_USR			EQU		0x32000000
SP_SYS			EQU		0x32000000
SP_SVC			EQU		0x1fff5000
SP_IRQ			EQU		0x31f00000
SP_FIQ			EQU		0x32000000
SP_UND			EQU		0x32000000
SP_ABT			EQU		0x32000000


;******************************************************
;DEFINE THE INTERRUPT SOURCE  BEGIN
;******************************************************      
INTSRC_RTC  		EQU		0X80000000   	;    //31            15                                          
INTSRC_DMA          	EQU  	0X40000000		; ,    //30      14    
INTSRC_EMI         		EQU 	0X20000000		 ; ,    //29         13 
INTSRC_GPT        		EQU 	0X10000000		 ; ,    //28        12
INTSRC_USB      		EQU 	0X08000000		 ; ,    //27        11
INTSRC_SPI      		EQU 	0X04000000 		; ,    //26         10
INTSRC_MMC        		EQU 	0X02000000		 ; ,    //25        9
INTSRC_UART1         	EQU 	0X01000000		 ; ,    //24        8
INTSRC_UART2        	EQU 	0X00800000		 ; ,    //23        7
INTSRC_I2C         		EQU 	0X00400000		 ; ,    //22        6
INTSRC_AC97          	EQU 	0X00200000		 ;,    //21         5
INTSRC_MMA     		EQU 	0X00100000		 ; ,    //20        4
INTSRC_EXTINT17     	EQU 	0X00080000		 ; ,    //19        3
INTSRC_EXTINT16        EQU 	0X00040000 		; ,    //18         2
INTSRC_EXTINT15   	EQU 	0X00020000		 ; ,    //17  1      
;OFF1'B0               		EQU  	0X00010000		 ; ,    //16  		0	        
INTSRC_EXTINT0          EQU 	0X00008000 		; ,    //15      			    
INTSRC_EXTINT1          EQU 	0X00004000		 ; ,    //14      			    
INTSRC_EXTINT2          EQU 	0X00002000 		; ,    //13      			    
INTSRC_EXTINT3          EQU 	0X00001000 		; ,    //12      			    
INTSRC_EXTINT4          EQU 	0X00000800		 ; ,    //11      			    
INTSRC_EXTINT5          EQU 	0X00000400 		 ; ,    //10      			    
INTSRC_EXTINT6          EQU 	0X00000200		 ; ,    //9       			    
INTSRC_EXTINT7          EQU 	0X00000100		 ; ,    //8       			    
INTSRC_EXTINT8          EQU 	0X00000080		 ; ,    //7       			    
INTSRC_EXTINT9          EQU 	0X00000040		 ; ,    //6       			    
INTSRC_EXTINT10         EQU 	0X00000020		 ; ,    //5       			    
INTSRC_EXTINT11         EQU 	0X00000010		 ; ,    //4       			    
INTSRC_EXTINT12         EQU 	0X00000008		 ; ,    //3       			    
INTSRC_EXTINT13         EQU 	0X00000002 		; ,    //2       			    
INTSRC_EXTINT14          EQU 	0X00000001 		; ,    //1       			    




	END