hardware.h

基于arm嵌入式处理器的USB驱动代码及详细pdf中文手册

                                      // class 6 */                                                      
#define MMC_SET_WRITE_PROT       28   	// ac   [31:0] data addr   R1b 
#define MMC_CLR_WRITE_PROT       29   	// ac   [31:0] data addr   R1b 
#define MMC_SEND_WRITE_PROT      30   	// adtc [31:0] wpdata addr R1  
                                                                     
                                          // class 7 */
#define MMC_LOCK_UNLOCK          42   		// adtc                    R1b 

                                            //class 8 */
#define MMC_IO_RW_DIRECT         53   		//                         R5  
#define MMC_IO_RW_EXTEND         54   		//                        R5  
#define MMC_APP_CMD              55   		// ac   [31:16] RCA        R1  
#define MMC_GEN_CMD              56   		//adtc [0] RD/WR          R1b

                                       // class 9 */                                                       
#define MMC_FAST_IO              39   			// ac   <Complex>          R4   
#define MMC_GO_IRQ_STATE         40   		// bcr                     R5                                                       
                  
                                                    
                                                    
#define R1_OUT_OF_RANGE		(1 << 31)       /* er, c */                  
#define R1_ADDRESS_ERROR	(1 << 30)	/* erx, c */                         
#define R1_BLOCK_LEN_ERROR	(1 << 29)	/* er, c */                                  
#define R1_ERASE_SEQ_ERROR      (1 << 28)	/* er, c */                                  
#define R1_ERASE_PARAM		(1 << 27)	/* ex, c */                                  
#define R1_WP_VIOLATION		(1 << 26)	/* erx, c */                     
#define R1_COM_CRC_ERROR	(1 << 23)	/* er, b */                          
#define R1_ILLEGAL_COMMAND	(1 << 22)	/* er, b */                                  
#define R1_ERROR		(1 << 19)	/* erx, c */                         
#define R1_stream_read_sustain		(1 << 18)	/* ex, c */                                  
#define R1_stream_write_sustain		(1 << 17)	/* ex, c */                                  
#define R1_CID_CSD_OVERWRITE	(1 << 16)	/* erx, c, CID/CSD overwrite */     
#define R1_WP_ERASE_SKIP	(1 << 15)	/* sx, c */                         
#define R1_ERASE_RESET		(1 << 13)	/* sr, c */                         
#define R1_READY_FOR_DATA	(1 << 8)	/* sx, a */                         	               

                                         
                                         
 enum mmc_result_t {                        	               
 	MMC_NO_RESPONSE        = -1, 
 	MMC_NO_ERROR           = 0,  
 	MMC_ERROR_OUT_OF_RANGE,      
 	MMC_ERROR_ADDRESS,           
 	MMC_ERROR_BLOCK_LEN,         
 	MMC_ERROR_ERASE_SEQ,         
 	MMC_ERROR_ERASE_PARAM,       
 	MMC_ERROR_WP_VIOLATION,      
 	MMC_ERROR_CARD_IS_LOCKED,    
 	MMC_ERROR_LOCK_UNLOCK_FAILED,
 	MMC_ERROR_COM_CRC,           
 	MMC_ERROR_ILLEGAL_COMMAND,   
 	MMC_ERROR_CARD_ECC_FAILED,   
 	MMC_ERROR_CC,                
 	MMC_ERROR_GENERAL,           
 	MMC_ERROR_UNDERRUN,          
 	MMC_ERROR_OVERRUN,           
 	MMC_ERROR_CID_CSD_OVERWRITE, 
 	MMC_ERROR_STATE_MISMATCH,    
 	MMC_ERROR_HEADER_MISMATCH,   
 	MMC_ERROR_TIMEOUT,           
 	MMC_ERROR_CRC,               
 	MMC_ERROR_DRIVER_FAILURE=21,
  	MMC_OCR_ERROR=99     
 };
 enum mmcc_result_t { 
 	END_CMD_RESP=55, 
 	TIME_OUT_RESP=66,
 	RESP_CRC_ERR=77, 
 	CRC_ERROR=88,
 	Tx_Fifo_Read_Error,
 	Rx_Fifo_Write_Error,
 	TIME_OUT_READ=99
 };                                         
  
                                        
                                                    
/****************************************
	functions for all modules
****************************************/

/*RTC*/
extern void init_rtc(void);
extern ER set_ymd(U32 year, U32 month, U32 day);
extern ER set_hms(U32 hour, U32 minute, U32 second);
extern ER get_ymd(U32* year, U32 * month, U32* day);
extern ER get_hms(U32* hour, U32* minute, U32* second);
extern ER set_alarmtime(U32 hour, U32 minute);
extern ER rtc_int_en(BOOL alarm, BOOL wdog, BOOL samp, BOOL minroll, BOOL secroll);
extern ER set_samp(U32 frequency);
extern ER set_wdog_cont(U32 count);
extern ER int_serv_rtc(void);

/*UART*/
extern ER init_uart1(U32 sysclk, U32 baudrate, U32 databit, U32 trigerlevel );
extern ER uart_int_en(U32 recie, U32  thrie);
extern ER int_serv_uart1(void);
extern ER HA_WR_UART1( U32  DATA  );

/*GPT*/
extern ER init_gpt1(void);
extern ER gpt_int_en(U32 comp);
extern ER int_serv_gpt1(void);

/*PWM*/
extern ER init_pwm1(void);
extern ER int_serv_pwm(void);

/*LCDC*/
extern ER init_lcdc(void);  
extern ER lcd_draw(U8 x1, U8 y1, U8 x2, U8 y2, U8 color);
extern ER meiz(void);
extern ER turn(void);

/*INTC*/
extern ER init_intc( void );

/*GPIO*/
void port_test(void);

#define set_plevel(plevel)		\
	*(RP)INTC_IPLV =  plevel

#define set_int_force(intnum)		\
	*(RP)INTC_IFCE = (1 << intnum)
	
#define irq_enable(intnum)	\
	*(RP)INTC_IEN |= (1 << intnum)

#define irq_disable( intnum)	\
	*(RP)INTC_IEN &= ~(1<< intnum)
	
#define mask_irq(intnum)		\
	*(RP)INTC_IMSK |= (1 << intnum)
	
#define unmask_irq(intnum)	\
	*(RP)INTC_IMSK &= ~(1 << intnum)

#define mask_all_irq() 	\
	*(RP)INTC_IMSK = 0xFFFFFFFF

#define unmask_all_irq()		\
	*(RP)INTC_IMSK = 0x00000000

#define enable_all_irq()		\
	*(RP)INTC_IEN = 0XFFFFFFFF

#define disable_all_irq()	\
	*(RP)INTC_IEN = 0X00000000


/*SPI*/
extern ER HA_INITSPI(void);
extern ER HA_SPI_HANDLE(void);
extern ER usbinit(void);


/*EMI*/ 
U32 HA_INIT_EMI(U32 gloabalvar_add);
ER  clear(U32 tempadd, U32 num);
ER  HA_EMI_WRIT(U32 add, U32 data);
ER  HA_DMA_DATADEFINE(U32 beginadd, U32 num, U32 size);
U32 HA_DMA_DATADCHECK(U32 beginadd, U32 num, U32 size, U32 gloabalvar_add)	;

U32 HA_INIT_NANDFLASH(U32 gloabalvar_add);
ER HA_NAND_READ(void);
ER HA_NAND_WRIT(void);

ER HA_NandFlash(void);
ER HA_NandFlash_IdRead(U32 gloabalvar_add);
ER HA_NandFlash_BadBlcokHandler(void);


ER NorFlash_write( U32 Pageadd, U32 data );
ER NorFlash_read( U32 address);
ER NorFlash_unlock( U32 address);
ER NorFlash_idlejud(U32 address);
ER NorFlash_clearSR(void);
ER NorFlash_bolckerase(U32 blockadd);
ER NorFlash_Normal(U32 address);


/*DMA*/
ER HA_InitDMAC(void);
ER HA_DMA_INITIAL_ONECHANNEL(U32  channelnum);
ER HA_DMA_TRANS(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
ER HA_DMA_TRANS_RX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
ER HA_DMA_TRANS_TX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);




/*MMC*/
extern  ER init_mmc(void );
extern  ER Send_Cmd_Wait_Resp(U32 cmd,U32 arg,U32 com_dat_cont,U32 blk_len,U32 nob,U32 int_mask);
extern  ER Mmc_Software_Reset( void);
extern  ER Card_Registry(void);
extern  ER Mmc_Block_Write_Dma(U32 nob,U32 address);
extern  ER Mmc_Block_Read_Dma(U32 nob,U32 address);
extern  ER Check_Card_Status(void);
extern  ER Block_Write_polling(U32 rca,U32 nob,U32 address);
extern  ER Block_Read_Polling(U32 rca,U32 nob,U32 address);
extern  ER Stream_Read(U32 nob,U32 address);
extern   ER Stream_Write(U32 nob,U32 address);
extern   ER Write_Reg( U32 reg,U32 data);
extern  ER Read_Reg(U32 reg);
extern  ER MmcCard_Chect(void); 
extern  ER Check_Ocr_Reg(void);
extern HA_DMA_TRANS_RX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);
extern HA_DMA_TRANS_TX(U32 srcadd, U32 destadd, U32 srcwidth, U32 destwidth, U32 srcsize, U32 channelnum, U32 transnum);






/****************************************
	macros  for write and read registers
****************************************/
#define write_reg(reg, data) \
	*(RP)reg = data

#define read_reg(reg) \
	*(RP)reg

/****************************************
	for print function
****************************************/

extern ER print( U32 addr, U32 errsymb );
extern ER print_num( U32 addr, U32 num );
extern ER prints(char *s);


#endif