📄 main.lst
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36: IOCLR0 = input_buffer[0];
00000056 4800 LDR R0,=input_buffer ; input_buffer
00000058 7800 LDRB R0,[R0,#0x0] ; input_buffer
0000005A 1C01 MOV R1,R0
0000005C 4800 LDR R0,=0xE002800C
0000005E 6001 STR R1,[R0,#0x0]
41: }
00000060 L_5:
00000060 E7FE B L_5 ; T=0x00000060
00000062 ; SCOPE-END
42: }
00000062 B002 ADD R13,#0x8
00000064 BC08 POP {R3}
00000066 4718 BX R3
00000068 ENDP ; 'main'
*** CODE SEGMENT '?PR?SPI_write?T?main':
45: void SPI_write(unsigned char *buffer,unsigned char bytecount)
00000000 B410 PUSH {R4}
00000002 1C0B MOV R3,R1 ; bytecount
00000004 ---- Variable 'bytecount' assigned to Register 'R3' ----
00000004 1C04 MOV R4,R0 ; buffer
00000006 ---- Variable 'buffer' assigned to Register 'R4' ----
47: lock = 1;
00000006 2201 MOV R2,#0x1
00000008 4800 LDR R0,=lock ; lock
ARM COMPILER V2.53, main 22/03/07 15:22:54 PAGE 6
0000000A 7002 STRB R2,[R0,#0x0] ; lock
48: SPI_buffer = buffer;
0000000C 1C21 MOV R1,R4 ; buffer
0000000E 4800 LDR R0,=SPI_buffer ; SPI_buffer
00000010 6001 STR R1,[R0,#0x0] ; SPI_buffer
49: SPI_bytecount = bytecount;
00000012 1C19 MOV R1,R3 ; bytecount
00000014 4800 LDR R0,=SPI_bytecount ; SPI_bytecount
00000016 7001 STRB R1,[R0,#0x0] ; SPI_bytecount
50: IOCLR0 = 0x00000400; //Pull Chipselect low
00000018 4800 LDR R1,=0x400
0000001A 4800 LDR R0,=0xE002800C
0000001C 6001 STR R1,[R0,#0x0]
51: S0SPDR = 0x00000006; //Send WRITE opcode
0000001E 2106 MOV R1,#0x6
00000020 4800 LDR R0,=0xE0020008
00000022 7001 STRB R1,[R0,#0x0]
52: status = 0x01; //set next state
00000024 4800 LDR R0,=status ; status
00000026 7002 STRB R2,[R0,#0x0] ; status
53: }
00000028 BC10 POP {R4}
0000002A 4770 BX R14
0000002C ENDP ; 'SPI_write?T'
*** CODE SEGMENT '?PR?SPI_read?T?main':
55: void SPI_read(unsigned char *buffer,unsigned char bytecount)
00000000 1C0A MOV R2,R1 ; bytecount
00000002 ---- Variable 'bytecount' assigned to Register 'R2' ----
00000002 1C03 MOV R3,R0 ; buffer
00000004 ---- Variable 'buffer' assigned to Register 'R3' ----
57: SPI_buffer = buffer;
00000004 1C19 MOV R1,R3 ; buffer
00000006 4800 LDR R0,=SPI_buffer ; SPI_buffer
00000008 6001 STR R1,[R0,#0x0] ; SPI_buffer
58: SPI_bytecount = bytecount;
0000000A 1C11 MOV R1,R2 ; bytecount
0000000C 4800 LDR R0,=SPI_bytecount ; SPI_bytecount
0000000E 7001 STRB R1,[R0,#0x0] ; SPI_bytecount
59: IOCLR0 = 0x00000400; //Pull Chipselect low
00000010 4800 LDR R1,=0x400
00000012 4800 LDR R0,=0xE002800C
00000014 6001 STR R1,[R0,#0x0]
60: S0SPDR = 0x00000003; //Send READ code
00000016 2103 MOV R1,#0x3
00000018 4800 LDR R0,=0xE0020008
0000001A 7001 STRB R1,[R0,#0x0]
61: status = 0x05; //set next state
0000001C 2105 MOV R1,#0x5
0000001E 4800 LDR R0,=status ; status
00000020 7001 STRB R1,[R0,#0x0] ; status
62: }
00000022 4770 BX R14
00000024 ENDP ; 'SPI_read?T'
*** CODE SEGMENT '?PR?SPI_ISR?A?main':
65: void SPI_ISR (void) __irq
00000000 E92D0007 STMDB R13!,{R0-R2}
66: {
00000004 ; SCOPE-START
70: switch(status)
00000004 E5100000 LDR R0,=status ; status
00000008 E5D00000 LDRB R0,[R0,#0x0] ; status
0000000C E3500002 CMP R0,#0x0002
00000010 0A000011 BEQ L_12 ; Targ=0x5C
00000014 E3500003 CMP R0,#0x0003
00000018 0A000016 BEQ L_13 ; Targ=0x78
0000001C E3500004 CMP R0,#0x0004
ARM COMPILER V2.53, main 22/03/07 15:22:54 PAGE 7
00000020 0A00002A BEQ L_14 ; Targ=0xD0
00000024 E3500005 CMP R0,#0x0005
00000028 0A000032 BEQ L_15 ; Targ=0xF8
0000002C E3500006 CMP R0,#0x0006
00000030 0A000037 BEQ L_16 ; Targ=0x114
00000034 E3500007 CMP R0,#0x0007
00000038 0A000050 BEQ L_17 ; Targ=0x180
0000003C E3500001 CMP R0,#0x0001
00000040 1A000051 BNE L_9 ; Targ=0x18C
72: case (0x01):
00000044 L_10:
74: S0SPDR = 0x00000002;
00000044 E3A01002 MOV R1,#0x2
00000048 E5100000 LDR R0,=0xE0020008
0000004C E5C01000 STRB R1,[R0,#0x0]
75: status = 0x02; //set next state
00000050 E5100000 LDR R0,=status ; status
00000054 E5C01000 STRB R1,[R0,#0x0] ; status
76: break;
00000058 EA00004B B L_9 ; Targ=0x18C
78: case (0x02): //Send Write Address
0000005C L_12:
79: S0SPDR = 0x00000000;
0000005C E3A01000 MOV R1,#0x0
00000060 E5100000 LDR R0,=0xE0020008
00000064 E5C01000 STRB R1,[R0,#0x0]
80: status = 0x03; //Set next state
00000068 E3A01003 MOV R1,#0x3
0000006C E5100000 LDR R0,=status ; status
00000070 E5C01000 STRB R1,[R0,#0x0] ; status
81: break;
00000074 EA000044 B L_9 ; Targ=0x18C
83: case (0x03): //write data
00000078 L_13:
84: S0SPDR = *SPI_buffer++;
00000078 E5101000 LDR R1,=SPI_buffer ; SPI_buffer
0000007C E5910000 LDR R0,[R1,#0x0] ; SPI_buffer
00000080 E2802001 ADD R2,R0,#0x0001
00000084 E5812000 STR R2,[R1,#0x0] ; SPI_buffer
00000088 E5D01000 LDRB R1,[R0,#0x0]
0000008C E5100000 LDR R0,=0xE0020008
00000090 E5C01000 STRB R1,[R0,#0x0]
85: if( --SPI_bytecount)
00000094 E5101000 LDR R1,=SPI_bytecount ; SPI_bytecount
00000098 E5D10000 LDRB R0,[R1,#0x0] ; SPI_bytecount
0000009C E2400001 SUB R0,R0,#0x0001
000000A0 E20000FF AND R0,R0,#0x00FF
000000A4 E5C10000 STRB R0,[R1,#0x0] ; SPI_bytecount
000000A8 E3500000 CMP R0,#0x0000
000000AC 0A000003 BEQ L_18 ; Targ=0xC0
87: status = 0x03; //Set Next state
000000B0 E3A01003 MOV R1,#0x3
000000B4 E5100000 LDR R0,=status ; status
000000B8 E5C01000 STRB R1,[R0,#0x0] ; status
88: }
000000BC EA000032 B L_9 ; Targ=0x18C
000000C0 L_18:
91: status = 0x04; //End condition
000000C0 E3A01004 MOV R1,#0x4
000000C4 E5100000 LDR R0,=status ; status
000000C8 E5C01000 STRB R1,[R0,#0x0] ; status
93: break;
000000CC EA00002E B L_9 ; Targ=0x18C
95: case (0x04): //End condition
000000D0 L_14:
96: S0SPDR = 0x00000055; //Need this dummy write for simulation
ARM COMPILER V2.53, main 22/03/07 15:22:54 PAGE 8
000000D0 E3A01055 MOV R1,#0x55
000000D4 E5100000 LDR R0,=0xE0020008
000000D8 E5C01000 STRB R1,[R0,#0x0]
97: IOSET0 = 0x00000400; //Pull Chipselect high
000000DC E3A01B01 MOV R1,#0x400
000000E0 E5100000 LDR R0,=0xE0028004
000000E4 E5801000 STR R1,[R0,#0x0]
98: status = 0x07; //jump to null case
000000E8 E3A01007 MOV R1,#0x7
000000EC E5100000 LDR R0,=status ; status
000000F0 E5C01000 STRB R1,[R0,#0x0] ; status
99: break;
000000F4 EA000024 B L_9 ; Targ=0x18C
102: case (0x05):
000000F8 L_15:
103: S0SPDR = 0x00000000; //Send Address
000000F8 E3A01000 MOV R1,#0x0
000000FC E5100000 LDR R0,=0xE0020008
00000100 E5C01000 STRB R1,[R0,#0x0]
104: status = 0x06; //set next state
00000104 E3A01006 MOV R1,#0x6
00000108 E5100000 LDR R0,=status ; status
0000010C E5C01000 STRB R1,[R0,#0x0] ; status
105: break;
00000110 EA00001D B L_9 ; Targ=0x18C
107: case (0x06):
00000114 L_16:
108: *SPI_buffer = S0SPDR; //read data
00000114 E5100000 LDR R0,=0xE0020008
00000118 E5D01000 LDRB R1,[R0,#0x0]
0000011C E5100000 LDR R0,=SPI_buffer ; SPI_buffer
00000120 E5900000 LDR R0,[R0,#0x0] ; SPI_buffer
00000124 E5C01000 STRB R1,[R0,#0x0]
109: S0SPDR = 0xFF; //Send Address
00000128 E3A010FF MOV R1,#0xFF
0000012C E5100000 LDR R0,=0xE0020008
00000130 E5C01000 STRB R1,[R0,#0x0]
110: SPI_buffer++;
00000134 E5100000 LDR R0,=SPI_buffer ; SPI_buffer
00000138 E5901000 LDR R1,[R0,#0x0] ; SPI_buffer
0000013C E2811001 ADD R1,R1,#0x0001
00000140 E5801000 STR R1,[R0,#0x0] ; SPI_buffer
112: if( --SPI_bytecount)
00000144 E5101000 LDR R1,=SPI_bytecount ; SPI_bytecount
00000148 E5D10000 LDRB R0,[R1,#0x0] ; SPI_bytecount
0000014C E2400001 SUB R0,R0,#0x0001
00000150 E20000FF AND R0,R0,#0x00FF
00000154 E5C10000 STRB R0,[R1,#0x0] ; SPI_bytecount
00000158 E3500000 CMP R0,#0x0000
0000015C 0A000003 BEQ L_20 ; Targ=0x170
114: status = 0x06; //Set Next state
00000160 E3A01006 MOV R1,#0x6
00000164 E5100000 LDR R0,=status ; status
00000168 E5C01000 STRB R1,[R0,#0x0] ; status
115: }
0000016C EA000006 B L_9 ; Targ=0x18C
00000170 L_20:
118: status = 0x07; //End condition
00000170 E3A01007 MOV R1,#0x7
00000174 E5100000 LDR R0,=status ; status
00000178 E5C01000 STRB R1,[R0,#0x0] ; status
120: break;
0000017C EA000002 B L_9 ; Targ=0x18C
122: case (0x07) : //Null Case
00000180 L_17:
123: lock = 0;
ARM COMPILER V2.53, main 22/03/07 15:22:54 PAGE 9
00000180 E3A01000 MOV R1,#0x0
00000184 E5100000 LDR R0,=lock ; lock
00000188 E5C01000 STRB R1,[R0,#0x0] ; lock
129: }
0000018C L_9:
131: S0SPINT = 0x01; //Signal end of interrupt
0000018C E3A01001 MOV R1,#0x1
00000190 E5100000 LDR R0,=0xE002001C
00000194 E5C01000 STRB R1,[R0,#0x0]
132: VICVectAddr = 0x00000000; //Dummy write to signal end of interrupt
00000198 E3A01000 MOV R1,#0x0
0000019C E5100000 LDR R0,=0xFFFFF030
000001A0 E5801000 STR R1,[R0,#0x0]
000001A4 ; SCOPE-END
000001A4 E8BD0007 LDMIA R13!,{R0-R2}
000001A8 E25EF004 SUBS R15,R14,#0x0004
000001AC ENDP ; 'SPI_ISR?A'
Module Information Static
----------------------------------
code size = ------
data size = 15
const size = 8
End of Module Information.
ARM COMPILATION COMPLETE. 2 WARNING(S), 0 ERROR(S)
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