can_tx.lst

一个基于LPC21平台的CAN总线接收与发送实现源代码.

ARM COMPILER V2.00f,  CAN_TX                                                               20/02/05  14:46:37  PAGE 1   


ARM COMPILER V2.00f, COMPILATION OF MODULE CAN_TX
OBJECT MODULE PLACED IN CAN_TX.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe CAN_TX.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG TABS(4) 

stmt  level    source

    1          #include <LPC21xx.H>
    2          
    3          void init_CAN2(void);
    4          void TX_CAN2(void);
    5          
    6          void init_CAN2(void)
    7          {
    8   1      ADCR        =       0x00270601;         //Setup A/D: 10-bit AIN0 @ 3MHz 
    9   1      ADCR        |=      0x01000000;         //Start A/D Conversion 
   10   1                                              
   11   1      
   12   1      PINSEL1     |=      0x00014000;         //Enable Pin 0.25 as CAN1 RX
   13   1      C2MOD       =       0x00000001;         //Set CAN controller into reset
   14   1      C2BTR       =       0x001C001D;         //Set bit timing to 125k
   15   1      C2MOD       =       0x00000000;         //Release CAN controller
   16   1      }
   17          
   18          void TX_CAN2(void)
   19          {
   20   1      unsigned int val;
   21   1      C2TFI1      =       0x00040000;         //Set DLC to 4 bytes    
   22   1      C2TID1      =       0x00000002;         //Set address to 2 Standard Frame
   23   1      
   24   1      do
   25   1      {
   26   2      val         =       ADDR;               // Read A/D Data Register 
   27   2      }        
   28   1      while ((val & 0x80000000) == 0);
   29   1                                              //A to D conversion 
   30   1      
   31   1      if(C2SR & 0x00000004)                   //See if Tx Buffer 1 is free
   32   1      {
   33   2      
   34   2      C2TDA1      =       val;                //Copy A/D result into first four bytes
   35   2      C2CMR       =       0x00000021;         //Transmit the message
   36   2      }
   37   1      }
ARM COMPILER V2.00f,  CAN_TX                                                               20/02/05  14:46:37  PAGE 2   

ASSEMBLY LISTING OF GENERATED OBJECT CODE



*** PUBLICS:
 PUBLIC         init_CAN2?T
 PUBLIC         TX_CAN2?T



*** CODE SEGMENT '?PR?init_CAN2?T?CAN_TX':
    8: ADCR           =       0x00270601;         //Setup A/D: 10-bit AIN0 @ 3MHz 
 00000000  4800      LDR         R1,=0x270601
 00000002  4800      LDR         R0,=0xE0034000
 00000004  6001      STR         R1,[R0,#0x0]
    9: ADCR         |=      0x01000000;         //Start A/D Conversion 
 00000006  4800      LDR         R2,=0x1000000
 00000008  4800      LDR         R0,=0xE0034000
 0000000A  6801      LDR         R1,[R0,#0x0]
 0000000C  4311      ORR         R1,R2
 0000000E  6001      STR         R1,[R0,#0x0]
   12: PINSEL1     |=      0x00014000;         //Enable Pin 0.25 as CAN1 RX
 00000010  4800      LDR         R2,=0x14000
 00000012  4800      LDR         R0,=0xE002C004
 00000014  6801      LDR         R1,[R0,#0x0]
 00000016  4311      ORR         R1,R2
 00000018  6001      STR         R1,[R0,#0x0]
   13: C2MOD         =       0x00000001;         //Set CAN controller into reset
 0000001A  2101      MOV         R1,#0x1
 0000001C  4800      LDR         R0,=0xE0048000
 0000001E  6001      STR         R1,[R0,#0x0]
   14: C2BTR         =       0x001C001D;         //Set bit timing to 125k
 00000020  4800      LDR         R1,=0x1C001D
 00000022  4800      LDR         R0,=0xE0048014
 00000024  6001      STR         R1,[R0,#0x0]
   15: C2MOD         =       0x00000000;         //Release CAN controller
 00000026  2100      MOV         R1,#0x0
 00000028  4800      LDR         R0,=0xE0048000
 0000002A  6001      STR         R1,[R0,#0x0]
   16: }
 0000002C  4770      BX          R14
 0000002E          ENDP ; 'init_CAN2?T'


*** CODE SEGMENT '?PR?TX_CAN2?T?CAN_TX':
   19: {
 00000000            ; SCOPE-START
   21: C2TFI1         =       0x00040000;         //Set DLC to 4 bytes    
 00000000  4800      LDR         R1,=0x40000
 00000002  4800      LDR         R0,=0xE0048030
 00000004  6001      STR         R1,[R0,#0x0]
   22: C2TID1         =       0x00000002;         //Set address to 2 Standard Frame
 00000006  2102      MOV         R1,#0x2
 00000008  4800      LDR         R0,=0xE0048034
 0000000A  6001      STR         R1,[R0,#0x0]
   24: do
 0000000C          L_1:
   26: val         =       ADDR;               // Read A/D Data Register 
 0000000C  4800      LDR         R0,=0xE0034004
 0000000E  6801      LDR         R1,[R0,#0x0]
 00000010  ---- Variable 'val' assigned to Register 'R1' ----
   27: }         
 00000010  4800      LDR         R0,=0x80000000
 00000012  4201      TST         R1,R0 ; val
 00000014  D0FA      BEQ         L_1  ; T=0x0000000C
   31: if(C2SR & 0x00000004)                   //See if Tx Buffer 1 is free
 00000016  4800      LDR         R0,=0xE004801C
 00000018  6800      LDR         R0,[R0,#0x0]
 0000001A  2204      MOV         R2,#0x4
 0000001C  4210      TST         R0,R2
 0000001E  D004      BEQ         L_5  ; T=0x0000002A
ARM COMPILER V2.00f,  CAN_TX                                                               20/02/05  14:46:37  PAGE 3   

   34: C2TDA1        =       val;                //Copy A/D result into first four bytes
 00000020  4800      LDR         R0,=0xE0048038
 00000022  6001      STR         R1,[R0,#0x0]
   35: C2CMR         =       0x00000021;         //Transmit the message
 00000024  2121      MOV         R1,#0x21
 00000026  4800      LDR         R0,=0xE0048004
 00000028  6001      STR         R1,[R0,#0x0]
   36: }
 0000002A          L_5:
 0000002A            ; SCOPE-END
 0000002A  4770      BX          R14
 0000002C          ENDP ; 'TX_CAN2?T'



Module Information          Static
----------------------------------
  code size            =    ------
  data size            =    ------
  const size           =    ------
End of Module Information.


ARM COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)