📄 main.lst
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00000014 4800 LDR R2,=0x40000
00000016 4800 LDR R0,=0xE002C004
00000018 6801 LDR R1,[R0,#0x0]
0000001A 4311 ORR R1,R2
0000001C 6001 STR R1,[R0,#0x0]
45: C1MOD = 0x00000001; //Set CAN controller into reset
0000001E 2101 MOV R1,#0x1
00000020 4800 LDR R0,=0xE0044000
00000022 6001 STR R1,[R0,#0x0]
46: C1BTR = 0x001C001D; //Set bit timing to 125k
00000024 4800 LDR R1,=0x1C001D
00000026 4800 LDR R0,=0xE0044014
00000028 6001 STR R1,[R0,#0x0]
47: C1IER = 0x00000001; //Enable the Receive interrupt
0000002A 2101 MOV R1,#0x1
0000002C 4800 LDR R0,=0xE0044010
0000002E 6001 STR R1,[R0,#0x0]
48: VICVectCntl0 = 0x0000003A; //select a priority slot for a given interrupt
00000030 213A MOV R1,#0x3A
00000032 4800 LDR R0,=0xFFFFF200
00000034 6001 STR R1,[R0,#0x0]
49: VICVectAddr0 = (unsigned)CAN1IRQ; //pass the address of the IRQ into the VIC slot
ARM COMPILER V2.00f, main 20/02/05 14:46:36 PAGE 4
00000036 4900 LDR R1,=CAN1IRQ?A ; CAN1IRQ?A
00000038 4800 LDR R0,=0xFFFFF100
0000003A 6001 STR R1,[R0,#0x0]
50: VICIntEnable = 0x04000000; //enable interrupt
0000003C 4800 LDR R1,=0x4000000
0000003E 4800 LDR R0,=0xFFFFF010
00000040 6001 STR R1,[R0,#0x0]
51: AFMR = 0x00000001; //Disable the Acceptance filters to allow setup of the table
00000042 2101 MOV R1,#0x1
00000044 4800 LDR R0,=0xE003C000
00000046 6001 STR R1,[R0,#0x0]
52: StandardFilter[0] = 0x20012002;
00000048 4800 LDR R1,=0x20012002
0000004A 4800 LDR R0,=StandardFilter ; StandardFilter
0000004C 6001 STR R1,[R0,#0x0] ; StandardFilter
53: StandardFilter[1] = 0x20032004;
0000004E 4800 LDR R1,=0x20032004
00000050 4800 LDR R0,=StandardFilter + 0x4 ; StandardFilter+4
00000052 6001 STR R1,[R0,#0x0] ; StandardFilter+4
54: GroupStdFilter[0] = 0x2009200F;
00000054 4800 LDR R1,=0x2009200F
00000056 4800 LDR R0,=GroupStdFilter ; GroupStdFilter
00000058 6001 STR R1,[R0,#0x0] ; GroupStdFilter
55: GroupStdFilter[1] = 0x20112020;
0000005A 4800 LDR R1,=0x20112020
0000005C 4800 LDR R0,=GroupStdFilter + 0x4 ; GroupStdFilter+4
0000005E 6001 STR R1,[R0,#0x0] ; GroupStdFilter+4
56: IndividualExtFilter[0] = 0x40010000;
00000060 4800 LDR R1,=0x40010000
00000062 4800 LDR R0,=IndividualExtFilter ; IndividualExtFilter
00000064 6001 STR R1,[R0,#0x0] ; IndividualExtFilter
57: IndividualExtFilter[1] = 0x40020000;
00000066 4800 LDR R1,=0x40020000
00000068 4800 LDR R0,=IndividualExtFilter + 0x4 ; IndividualExtFilter+4
0000006A 6001 STR R1,[R0,#0x0] ; IndividualExtFilter+4
58: GroupExtFilter[0] = 0x40030000;
0000006C 4800 LDR R1,=0x40030000
0000006E 4800 LDR R0,=GroupExtFilter ; GroupExtFilter
00000070 6001 STR R1,[R0,#0x0] ; GroupExtFilter
59: GroupExtFilter[2] = 0x40040000;
00000072 4800 LDR R1,=0x40040000
00000074 4800 LDR R0,=GroupExtFilter + 0x8 ; GroupExtFilter+8
00000076 6001 STR R1,[R0,#0x0] ; GroupExtFilter+8
60: SFF_sa = 0x00000000; //Set start address of Standard table
00000078 2100 MOV R1,#0x0
0000007A 4800 LDR R0,=0xE003C004
0000007C 6001 STR R1,[R0,#0x0]
61: SFF_GRP_sa = 0x00000010; //Set start address of Standard group table
0000007E 2110 MOV R1,#0x10
00000080 4800 LDR R0,=0xE003C008
00000082 6001 STR R1,[R0,#0x0]
62: EFF_sa = 0x00000018; //Set start address of Extended table
00000084 2118 MOV R1,#0x18
00000086 4800 LDR R0,=0xE003C00C
00000088 6001 STR R1,[R0,#0x0]
63: EFF_GRP_sa = 0x00000020; //Set start address of Extended group table
0000008A 2120 MOV R1,#0x20
0000008C 4800 LDR R0,=0xE003C010
0000008E 6001 STR R1,[R0,#0x0]
64: ENDofTable = 0x00000028; //Set end of table address
00000090 2128 MOV R1,#0x28
00000092 4800 LDR R0,=0xE003C014
00000094 6001 STR R1,[R0,#0x0]
65: AFMR = 0x00000000; //Enable Acceptance filters
00000096 2100 MOV R1,#0x0
00000098 4800 LDR R0,=0xE003C000
ARM COMPILER V2.00f, main 20/02/05 14:46:36 PAGE 5
0000009A 6001 STR R1,[R0,#0x0]
67: C1MOD = 0x00000000; //Release CAN controller
0000009C 2100 MOV R1,#0x0
0000009E 4800 LDR R0,=0xE0044000
000000A0 6001 STR R1,[R0,#0x0]
69: while(1)
000000A2 L_3:
71: TX_CAN2();
000000A2 F7FF BL TX_CAN2?T ; T=0x0001 (1)
000000A4 FFAD BL TX_CAN2?T ; T=0x0001 (2)
72: }
000000A8 E7FB B L_3 ; T=0x000000A2
000000AA BC08 POP {R3}
000000AC 4718 BX R3
000000AE ENDP ; 'main'
*** CODE SEGMENT '?PR?CAN1IRQ?A?main':
75: void CAN1IRQ (void) __irq
00000000 E92D0003 STMDB R13!,{R0-R1}
78: IOCLR1 = ~C1RDA<<8; //clear output pins
00000004 E5100000 LDR R0,=0xE0044028
00000008 E5901000 LDR R1,[R0,#0x0]
0000000C E1E01001 MVN R1,R1
00000010 E1A01401 MOV R1,R1,LSL #8
00000014 E5100000 LDR R0,=0xE002801C
00000018 E5801000 STR R1,[R0,#0x0]
79: IOSET1 = C1RDA<<8; //set output pins
0000001C E5100000 LDR R0,=0xE0044028
00000020 E5901000 LDR R1,[R0,#0x0]
00000024 E1A01401 MOV R1,R1,LSL #8
00000028 E5100000 LDR R0,=0xE0028014
0000002C E5801000 STR R1,[R0,#0x0]
80: C1CMR = 0x00000004; //release the recieve buffer
00000030 E3A01004 MOV R1,#0x4
00000034 E5100000 LDR R0,=0xE0044004
00000038 E5801000 STR R1,[R0,#0x0]
81: VICVectAddr = 0x00000000; //Signal the end of interrupt
0000003C E3A01000 MOV R1,#0x0
00000040 E5100000 LDR R0,=0xFFFFF030
00000044 E5801000 STR R1,[R0,#0x0]
82: }
00000048 E8BD0003 LDMIA R13!,{R0-R1}
0000004C E25EF004 SUBS R15,R14,#0x0004
00000050 ENDP ; 'CAN1IRQ?A'
Module Information Static
----------------------------------
code size = ------
data size = 32
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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