lian.syr

在ise下设计的蝶形变换程序

WARNING:Xst:1780 - Signal <sum> is never used or assigned.
WARNING:Xst:646 - Signal <cpsx<20:17>> is assigned but never used.
WARNING:Xst:646 - Signal <i<20>> is assigned but never used.
WARNING:Xst:646 - Signal <i<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <r<20>> is assigned but never used.
WARNING:Xst:646 - Signal <r<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <xmyc<20:17>> is assigned but never used.
WARNING:Xst:646 - Signal <sxtx<10:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sxty<10:9>> is assigned but never used.
WARNING:Xst:646 - Signal <xmy<10:9>> is assigned but never used.
WARNING:Xst:646 - Signal <cmsy<20:17>> is assigned but never used.
    Found 10-bit register for signal <i_out>.
    Found 10-bit register for signal <r_out>.
    Summary:
	inferred  20 D-type flip-flop(s).
Unit <ccmul> synthesized.


Synthesizing Unit <lian>.
    Related source file is "lian.vf".
Unit <lian> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                                          : 3
 9x8-bit multiplier                                    : 3
# Adders/Subtractors                                   : 3
 17-bit adder                                          : 1
 17-bit subtractor                                     : 1
 9-bit subtractor                                      : 1
# Registers                                            : 8
 10-bit register                                       : 2
 8-bit register                                        : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading module "jiajia.ngo" ( "jiajia.ngo" unchanged since last run )...
Reading module "jianjian.ngo" ( "jianjian.ngo" unchanged since last run )...
Loading core <jiajia> for timing and area information for instance <XLXI_2>.
Loading core <jianjian> for timing and area information for instance <XLXI_3>.
Loading core <jianjian> for timing and area information for instance <XLXI_4>.
Loading core <jiajia> for timing and area information for instance <XLXI_5>.
WARNING:Xst:2404 -  FFs/Latches <r_out<9:7>> (without init value) have a constant value of 0 in block <ccmul>.
WARNING:Xst:2404 -  FFs/Latches <i_out<9:7>> (without init value) have a constant value of 0 in block <ccmul>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Multipliers                                          : 3
 9x8-bit multiplier                                    : 3
# Adders/Subtractors                                   : 3
 17-bit adder                                          : 1
 17-bit subtractor                                     : 1
 9-bit subtractor                                      : 1
# Registers                                            : 22
 Flip-Flops                                            : 22

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment D:\xilinx.

Optimizing unit <lian> ...

Optimizing unit <ccmul> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lian, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lian.ngr
Top Level Output File Name         : lian
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 91

Cell Usage :
# BELS                             : 206
#      GND                         : 5
#      LUT1                        : 1
#      LUT2                        : 42
#      LUT4                        : 32
#      MUXCY                       : 70
#      VCC                         : 1
#      XORCY                       : 55
# FlipFlops/Latches                : 62
#      FD                          : 62
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 90
#      IBUF                        : 58
#      OBUF                        : 32
# MULTs                            : 3
#      MULT18X18                   : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      75  out of   3584     2%  
 Number of Slice Flip Flops:            62  out of   7168     0%  
 Number of 4 input LUTs:                75  out of   7168     1%  
 Number of bonded IOBs:                 91  out of    141    64%  
 Number of MULT18X18s:                   3  out of     16    18%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 62    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.478ns (Maximum Frequency: 223.314MHz)
   Minimum input arrival time before clock: 12.086ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 4.478ns (frequency: 223.314MHz)
  Total number of paths / destination ports: 437 / 32
-------------------------------------------------------------------------
Delay:               4.478ns (Levels of Logic = 10)
  Source:            XLXI_16/data_out_0 (FF)
  Destination:       XLXI_20/data_out_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_16/data_out_0 to XLXI_20/data_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.720   1.216  XLXI_16/data_out_0 (XLXI_16/data_out_0)
     begin scope: 'XLXI_4'
     LUT4:I0->O            1   0.551   0.000  BU3 (N2)
     MUXCY:S->O            1   0.500   0.000  BU4 (N5)
     MUXCY:CI->O           1   0.064   0.000  BU8 (N10)
     MUXCY:CI->O           1   0.064   0.000  BU12 (N15)
     MUXCY:CI->O           1   0.064   0.000  BU16 (N20)
     MUXCY:CI->O           1   0.064   0.000  BU20 (N25)
     MUXCY:CI->O           1   0.064   0.000  BU24 (N30)
     MUXCY:CI->O           0   0.064   0.000  BU28 (N35)
     XORCY:CI->O           1   0.904   0.000  BU32 (S<7>)
     end scope: 'XLXI_4'
     FD:D                      0.203          XLXI_20/data_out_7
    ----------------------------------------
    Total                      4.478ns (3.262ns logic, 1.216ns route)
                                       (72.8% logic, 27.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 20778 / 30
-------------------------------------------------------------------------
Offset:              12.086ns (Levels of Logic = 15)
  Source:            Bre_in<0> (PAD)
  Destination:       XLXI_1/r_out_0 (FF)
  Destination Clock: clk rising

  Data Path: Bre_in<0> to XLXI_1/r_out_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   1.216  Bre_in_0_IBUF (Bre_in_0_IBUF)
     LUT2:I0->O            1   0.551   0.000  XLXI_1/ccmul_xmy<0>lut (XLXI_1/N23)
     MUXCY:S->O            1   0.500   0.000  XLXI_1/ccmul_xmy<0>cy (XLXI_1/ccmul_xmy<0>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<1>cy (XLXI_1/ccmul_xmy<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<2>cy (XLXI_1/ccmul_xmy<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<3>cy (XLXI_1/ccmul_xmy<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<4>cy (XLXI_1/ccmul_xmy<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<5>cy (XLXI_1/ccmul_xmy<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  XLXI_1/ccmul_xmy<6>cy (XLXI_1/ccmul_xmy<6>_cyo)
     MUXCY:CI->O           0   0.064   0.000  XLXI_1/ccmul_xmy<7>cy (XLXI_1/ccmul_xmy<7>_cyo)
     XORCY:CI->O           1   0.904   0.801  XLXI_1/ccmul_xmy<8>_xor (XLXI_1/xmy<8>)
     MULT18X18:A8->P15     2   3.615   1.072  XLXI_1/mult_1/Mmult_result (XLXI_1/xmyc<15>)
     LUT2:I1->O            1   0.551   0.000  XLXI_1/ccmul_r<15>lut (XLXI_1/N46)
     MUXCY:S->O            0   0.500   0.000  XLXI_1/ccmul_r<15>cy (XLXI_1/ccmul_r<15>_cyo)
     XORCY:CI->O           1   0.904   0.000  XLXI_1/ccmul_r<16>_xor (XLXI_1/r<16>)
     FD:D                      0.203          XLXI_1/r_out_0
    ----------------------------------------
    Total                     12.086ns (8.997ns logic, 3.089ns route)
                                       (74.4% logic, 25.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              7.165ns (Levels of Logic = 1)
  Source:            XLXI_20/data_out_7 (FF)
  Destination:       Ere_out<7> (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_20/data_out_7 to Ere_out<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.720   0.801  XLXI_20/data_out_7 (XLXI_20/data_out_7)
     OBUF:I->O                 5.644          Ere_out_7_OBUF (Ere_out<7>)
    ----------------------------------------
    Total                      7.165ns (6.364ns logic, 0.801ns route)
                                       (88.8% logic, 11.2% route)

=========================================================================
CPU : 21.09 / 23.00 s | Elapsed : 22.00 / 23.00 s
 
--> 

Total memory usage is 116372 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   46 (   0 filtered)
Number of infos    :    0 (   0 filtered)