lian.syr

在ise下设计的蝶形变换程序

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.72 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.72 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: lian.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lian.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lian"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : lian
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lian.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ccmul.v" in library work
Compiling verilog include file "sub1.v"
Compiling verilog include file "mult.v"
Module <sub1> compiled
Compiling verilog include file "add.v"
Module <mult> compiled
Compiling verilog include file "sub2.v"
Module <add> compiled
Module <sub2> compiled
Compiling verilog file "yuan.v" in library work
Module <ccmul> compiled
Compiling verilog file "jianjian.v" in library work
Module <yuan> compiled
Compiling verilog file "jiajia.v" in library work
Module <jianjian> compiled
Compiling verilog file "dchufa.v" in library work
Module <jiajia> compiled
Compiling verilog file "chuli.v" in library work
Module <dchufa> compiled
Compiling verilog file "lian.vf" in library work
Module <chuli> compiled
Module <lian> compiled
No errors in compilation
Analysis of file <"lian.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:259 - "lian.vf" line 65 Connection to input port 'x_in' does not match port size
WARNING:HDLCompilers:259 - "lian.vf" line 66 Connection to input port 'y_in' does not match port size
WARNING:HDLCompilers:259 - "lian.vf" line 64 Connection to input port 'c_in' does not match port size
WARNING:HDLCompilers:259 - "lian.vf" line 63 Connection to input port 'cps_in' does not match port size
WARNING:HDLCompilers:259 - "lian.vf" line 62 Connection to input port 'cms_in' does not match port size
WARNING:HDLCompilers:261 - "lian.vf" line 68 Connection to output port 'r_out' does not match port size
WARNING:HDLCompilers:261 - "lian.vf" line 67 Connection to output port 'i_out' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 48 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 48 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 48 Connection to output port 'result' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 50 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 50 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 50 Connection to output port 'result' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 51 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 51 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 51 Connection to output port 'result' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 52 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 52 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 52 Connection to output port 'result' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 53 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 53 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 53 Connection to output port 'result' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 54 Connection to input port 'dataa' does not match port size
WARNING:HDLCompilers:259 - "ccmul.v" line 54 Connection to input port 'datab' does not match port size
WARNING:HDLCompilers:261 - "ccmul.v" line 54 Connection to output port 'result' does not match port size
Analyzing top module <lian>.
Module <lian> is correct for synthesis.
 
Analyzing module <ccmul>.
	w2 = 32'sb00000000000000000000000000010101
	w1 = 32'sb00000000000000000000000000001011
	w = 32'sb00000000000000000000000000001010
Module <ccmul> is correct for synthesis.
 
Analyzing module <sub1>.
	w1 = 32'sb00000000000000000000000000001001
Module <sub1> is correct for synthesis.
 
Analyzing module <mult>.
	w2 = 32'sb00000000000000000000000000010001
	w1 = 32'sb00000000000000000000000000001001
	w = 32'sb00000000000000000000000000001000
Module <mult> is correct for synthesis.
 
Analyzing module <add>.
	w2 = 32'sb00000000000000000000000000010001
Module <add> is correct for synthesis.
 
Analyzing module <sub2>.
	w2 = 32'sb00000000000000000000000000010001
Module <sub2> is correct for synthesis.
 
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Analyzing module <dchufa>.
Module <dchufa> is correct for synthesis.
 
Analyzing module <chuli>.
Module <chuli> is correct for synthesis.
 
Analyzing module <yuan>.
Module <yuan> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sub2>.
    Related source file is "sub2.v".
    Found 17-bit subtractor for signal <result>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <sub2> synthesized.


Synthesizing Unit <add>.
    Related source file is "add.v".
    Found 17-bit adder for signal <result>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <add> synthesized.


Synthesizing Unit <mult>.
    Related source file is "mult.v".
    Found 9x8-bit multiplier for signal <result>.
    Summary:
	inferred   1 Multiplier(s).
Unit <mult> synthesized.


Synthesizing Unit <sub1>.
    Related source file is "sub1.v".
    Found 9-bit subtractor for signal <result>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <sub1> synthesized.


Synthesizing Unit <yuan>.
    Related source file is "yuan.v".
Unit <yuan> synthesized.


Synthesizing Unit <chuli>.
    Related source file is "chuli.v".
WARNING:Xst:647 - Input <shu_in<0>> is never used.
Unit <chuli> synthesized.


Synthesizing Unit <dchufa>.
    Related source file is "dchufa.v".
    Found 8-bit register for signal <data_out>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <dchufa> synthesized.


Synthesizing Unit <ccmul>.
    Related source file is "ccmul.v".
WARNING:Xst:646 - Signal <cms<10:9>> is assigned but never used.
WARNING:Xst:646 - Signal <cps<10:9>> is assigned but never used.
WARNING:Xst:646 - Signal <c<9:8>> is assigned but never used.