_primary.vhd

来自「在ise下设计的蝶形变换程序」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity ccmul is
    generic(
        w2              : integer := 17;
        w1              : integer := 9;
        w               : integer := 8
    );
    port(
        clk             : in     vl_logic;
        x_in            : in     vl_logic_vector;
        y_in            : in     vl_logic_vector;
        c_in            : in     vl_logic_vector;
        cps_in          : in     vl_logic_vector;
        cms_in          : in     vl_logic_vector;
        r_out           : out    vl_logic_vector;
        i_out           : out    vl_logic_vector
    );
end ccmul;