_primary.vhd

来自「在ise下设计的蝶形变换程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity jianjian is
    port(
        A               : in     vl_logic_vector(7 downto 0);
        B               : in     vl_logic_vector(7 downto 0);
        B_IN            : in     vl_logic;
        S               : out    vl_logic_vector(7 downto 0)
    );
end jianjian;