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📄 1302-162.lst

📁 1302_18b20_8515基于AVR单片机的开发系统。 在使用中通过仿真来实现。可以将此程序扩展成其他外围设备的基础
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(0075) 	}
(0076) 
(0077) }
(0078) 
(0079) void init_lcd()     			//初始化
(0080) {
(0081) delay_ms(180);						//等待30ms以上
_init_lcd:
    01EE EB04      LDI	R16,0xB4
    01EF DF97      RCALL	_delay_ms
(0082) LCD_DATA_PORT=0x38;     		//8位2行5×7点阵
    01F0 E388      LDI	R24,0x38
    01F1 BB8B      OUT	0x1B,R24
(0083) command_enable();
    01F2 DFC0      RCALL	_command_enable
(0084) delay_us(100);					//等待39us以上
    01F3 E604      LDI	R16,0x64
    01F4 E010      LDI	R17,0
    01F5 DF9E      RCALL	_delay_us
(0085) LCD_DATA_PORT=0x0C;     		//显示器开、光标开、闪烁关
    01F6 E08C      LDI	R24,0xC
    01F7 BB8B      OUT	0x1B,R24
(0086) command_enable();
    01F8 DFBA      RCALL	_command_enable
(0087) delay_us(100);					//等待39us以上
    01F9 E604      LDI	R16,0x64
    01FA E010      LDI	R17,0
    01FB DF98      RCALL	_delay_us
(0088) LCD_DATA_PORT=0x01;     		//清屏
    01FC E081      LDI	R24,1
    01FD BB8B      OUT	0x1B,R24
(0089) command_enable();
    01FE DFB4      RCALL	_command_enable
(0090) delay_ms(10);						//等待1.53ms以上
    01FF E00A      LDI	R16,0xA
    0200 DF86      RCALL	_delay_ms
(0091) LCD_DATA_PORT=0x06;     		//输入方式
    0201 E086      LDI	R24,6
    0202 BB8B      OUT	0x1B,R24
(0092) command_enable();
    0203 DFAF      RCALL	_command_enable
(0093) delay_ms(180); 					//初始化完毕
    0204 EB04      LDI	R16,0xB4
    0205 DF81      RCALL	_delay_ms
    0206 9508      RET
FILE: D:\时钟芯片\1302\1302-162\18b20.c
(0001) #include <io8515v.h>
(0002) #include <macros.h>
(0003) #include <162-1302.h>
(0004) //时间延迟
(0005) void delayb(uint x)                //1.5us左右 
(0006) { 
_delayb:
  x                    --> R16
    0207 C002      RJMP	0x020A
(0007)      while(x) 
(0008)     { 
(0009)        x--; 
    0208 5001      SUBI	R16,1
    0209 4010      SBCI	R17,0
    020A 3000      CPI	R16,0
    020B 0701      CPC	R16,R17
    020C F7D9      BNE	0x0208
    020D 9508      RET
_init_1820:
  ack                  --> R20
    020E D0BB      RCALL	push_gset1
(0010)     } 
(0011) } 
(0012) //18b20初始化
(0013) uchar init_1820() 
(0014) {   uchar ack;
(0015)     B20_DATA_DDR|=B20_DATA_IO ;                   //输出   
    020F 9AA0      SBI	0x14,0
(0016)     B20_DATA_PORT&=~B20_DATA_IO ; 
    0210 98A8      CBI	0x15,0
(0017)     delayb(600);                   //复位低电平480us~960us
    0211 E508      LDI	R16,0x58
    0212 E012      LDI	R17,2
    0213 DFF3      RCALL	_delayb
(0018)     B20_DATA_PORT|=B20_DATA_IO ;                  //电平拉高
    0214 9AA8      SBI	0x15,0
(0019) 	B20_DATA_DDR&=~B20_DATA_IO ;                    //输入
    0215 98A0      CBI	0x14,0
(0020) 	delayb(90);                    //延时60us~240us
    0216 E50A      LDI	R16,0x5A
    0217 E010      LDI	R17,0
    0218 DFEE      RCALL	_delayb
(0021) 	ack=B20_DATA_PIN;                     //读出ack的值
    0219 B343      IN	R20,0x13
(0022) 	ack&=B20_DATA_IO; 
    021A 7041      ANDI	R20,1
(0023) 	delayb(200);                   //等待480us以上
    021B EC08      LDI	R16,0xC8
    021C E010      LDI	R17,0
    021D DFE9      RCALL	_delayb
(0024) 	B20_DATA_DDR|=B20_DATA_IO ;                   //输出   
    021E 9AA0      SBI	0x14,0
(0025) 	return(ack);
    021F 2F04      MOV	R16,R20
    0220 D0AC      RCALL	pop_gset1
    0221 9508      RET
_write_1820:
  m                    --> R20
  i                    --> R22
  x                    --> R10
    0222 D0A3      RCALL	push_gset3
    0223 2EA0      MOV	R10,R16
(0026) } 
(0027) //写一个字节
(0028) void write_1820(uchar x) 
(0029) {    
(0030)     uchar i,m;
(0031) 	B20_DATA_DDR|=B20_DATA_IO;   //输出 
    0224 9AA0      SBI	0x14,0
(0032)     for(i=0;i<8;i++) 
    0225 2766      CLR	R22
    0226 C01A      RJMP	0x0241
(0033)     {  
(0034) 	   m=x&0x01;                       
    0227 2D4A      MOV	R20,R10
    0228 7041      ANDI	R20,1
(0035) 	   if(m==0x01)
    0229 3041      CPI	R20,1
    022A F461      BNE	0x0237
(0036) 	   {
(0037) 	    delayb(1);                        //延时>1us
    022B E001      LDI	R16,1
    022C E010      LDI	R17,0
    022D DFD9      RCALL	_delayb
(0038)        	B20_DATA_PORT&=~B20_DATA_IO;    //产生写起始信号
    022E 98A8      CBI	0x15,0
(0039) 	   	delayb(3);                       //延时1us~15us  8us
    022F E003      LDI	R16,3
    0230 E010      LDI	R17,0
    0231 DFD5      RCALL	_delayb
(0040) 	   	B20_DATA_PORT|=B20_DATA_IO;     //数据线电平拉高
    0232 9AA8      SBI	0x15,0
(0041) 	   	delayb(55);                     //延时60us~120us  85us
    0233 E307      LDI	R16,0x37
    0234 E010      LDI	R17,0
    0235 DFD1      RCALL	_delayb
(0042) 	   }
    0236 C008      RJMP	0x023F
(0043) 	   else
(0044) 	   {
(0045) 	    delayb(1);                        //延时>1us
    0237 E001      LDI	R16,1
    0238 E010      LDI	R17,0
    0239 DFCD      RCALL	_delayb
(0046)        	B20_DATA_PORT&=~B20_DATA_IO;     //产生写起始信号
    023A 98A8      CBI	0x15,0
(0047)        	delayb(55);                      //B20采样要60us到120us  85us
    023B E307      LDI	R16,0x37
    023C E010      LDI	R17,0
    023D DFC9      RCALL	_delayb
(0048)        	B20_DATA_PORT|=B20_DATA_IO;      //数据线电平拉高
    023E 9AA8      SBI	0x15,0
(0049)        }
(0050) 	   x=x>>1;                          //右移一位
    023F 94A6      LSR	R10
    0240 9563      INC	R22
    0241 3068      CPI	R22,0x8
    0242 F320      BCS	0x0227
    0243 D07C      RCALL	pop_gset3
    0244 9508      RET
_read_1820:
  temp                 --> R20
  k                    --> R22
  n                    --> R10
    0245 D080      RCALL	push_gset3
(0051) 	} 
(0052) } 
(0053) //读一个字节
(0054) uchar read_1820() 
(0055) {     
(0056)     uchar temp,k,n; 
(0057)        temp=0; 
    0246 2744      CLR	R20
(0058)     for(n=0;n<8;n++) 
    0247 24AA      CLR	R10
    0248 C01E      RJMP	0x0267
(0059)        { 
(0060) 	  B20_DATA_DDR|=B20_DATA_IO;         //输出 
    0249 9AA0      SBI	0x14,0
(0061)       B20_DATA_PORT&=~B20_DATA_IO;               //产生读起始信号
    024A 98A8      CBI	0x15,0
(0062)       asm("nop");
    024B 0000      NOP
(0063) 	  asm("nop");
    024C 0000      NOP
(0064) 	  asm("nop");
    024D 0000      NOP
(0065) 	  asm("nop");                        //延时1us~15us  2us
    024E 0000      NOP
(0066)       B20_DATA_PORT|=B20_DATA_IO;        //电平拉高    
    024F 9AA8      SBI	0x15,0
(0067)       B20_DATA_DDR&=~B20_DATA_IO;        //接收数据
    0250 98A0      CBI	0x14,0
(0068) 	  asm("nop");                      //要在15us内完成读数
    0251 0000      NOP
(0069) 	  asm("nop");      
    0252 0000      NOP
(0070)       k=B20_DATA_PIN;     //读数据,从低位开始 
    0253 B363      IN	R22,0x13
(0071) 	  k&=0x01;
    0254 7061      ANDI	R22,1
(0072)       if(k) 
    0255 F029      BEQ	0x025B
(0073)       temp|=(1<<n); 
    0256 E001      LDI	R16,1
    0257 2D1A      MOV	R17,R10
    0258 D088      RCALL	lsl8
    0259 2B40      OR	R20,R16
    025A C006      RJMP	0x0261
(0074)       else 
(0075)       temp&=~(1<<n); 
    025B E001      LDI	R16,1
    025C 2D1A      MOV	R17,R10
    025D D083      RCALL	lsl8
    025E 2E20      MOV	R2,R16
    025F 9420      COM	R2
    0260 2142      AND	R20,R2
(0076)       delayb(40);                          //60~120us   
    0261 E208      LDI	R16,0x28
    0262 E010      LDI	R17,0
    0263 DFA3      RCALL	_delayb
(0077) 	  B20_DATA_DDR|=B20_DATA_IO;          //输出
    0264 9AA0      SBI	0x14,0
(0078)       B20_DATA_PORT|=B20_DATA_IO; 
    0265 9AA8      SBI	0x15,0
    0266 94A3      INC	R10
    0267 2D8A      MOV	R24,R10
    0268 3088      CPI	R24,0x8
    0269 F2F8      BCS	0x0249
(0079)    } 
(0080)    return temp; 
FILE: <library>
    026A 2F04      MOV	R16,R20
    026B D054      RCALL	pop_gset3
    026C 9508      RET
mod16s:
    026D 9468      BSET	6
    026E 92DA      ST	R13,-Y
    026F 2ED1      MOV	R13,R17
    0270 C004      RJMP	0x0275
div16s:
    0271 94E8      BCLR	6
    0272 92DA      ST	R13,-Y
    0273 2ED1      MOV	R13,R17
    0274 26D3      EOR	R13,R19
    0275 FF17      SBRS	R17,7
    0276 C004      RJMP	0x027B
    0277 9510      COM	R17
    0278 9500      COM	R16
    0279 5F0F      SUBI	R16,0xFF
    027A 4F1F      SBCI	R17,0xFF
    027B FF37      SBRS	R19,7
    027C C004      RJMP	0x0281
    027D 9530      COM	R19
    027E 9520      COM	R18
    027F 5F2F      SUBI	R18,0xFF
    0280 4F3F      SBCI	R19,0xFF
    0281 D00B      RCALL	xdiv16u
    0282 FED7      SBRS	R13,7
    0283 C004      RJMP	0x0288
    0284 9510      COM	R17
    0285 9500      COM	R16
    0286 5F0F      SUBI	R16,0xFF
    0287 4F1F      SBCI	R17,0xFF
    0288 90D9      LD	R13,Y+
    0289 9508      RET
mod16u:
    028A 9468      BSET	6
    028B C001      RJMP	xdiv16u
div16u:
    028C 94E8      BCLR	6
xdiv16u:
    028D 92EA      ST	R14,-Y
    028E 92FA      ST	R15,-Y
    028F 938A      ST	R24,-Y
    0290 24EE      CLR	R14
    0291 24FF      CLR	R15
    0292 E180      LDI	R24,0x10
    0293 0F00      LSL	R16
    0294 1F11      ROL	R17
    0295 1CEE      ROL	R14
    0296 1CFF      ROL	R15
    0297 16E2      CP	R14,R18
    0298 06F3      CPC	R15,R19
    0299 F018      BCS	0x029D
    029A 1AE2      SUB	R14,R18
    029B 0AF3      SBC	R15,R19
    029C 9503      INC	R16
    029D 958A      DEC	R24
    029E F7A1      BNE	0x0293
    029F F416      BRTC	0x02A2
    02A0 2D0E      MOV	R16,R14
    02A1 2D1F      MOV	R17,R15
    02A2 9189      LD	R24,Y+
    02A3 90F9      LD	R15,Y+
    02A4 90E9      LD	R14,Y+
    02A5 9508      RET
mod8u:
    02A6 9468      BSET	6
    02A7 C001      RJMP	xdiv8u
div8u:
    02A8 94E8      BCLR	6
xdiv8u:
    02A9 932A      ST	R18,-Y
    02AA 92FA      ST	R15,-Y
    02AB 92EA      ST	R14,-Y
    02AC 24FF      CLR	R15
    02AD 24EE      CLR	R14
    02AE E120      LDI	R18,0x10
    02AF 0F00      LSL	R16
    02B0 1CFF      ROL	R15
    02B1 1CEE      ROL	R14
    02B2 16E1      CP	R14,R17
    02B3 F010      BCS	0x02B6
    02B4 1AE1      SUB	R14,R17
    02B5 9503      INC	R16
    02B6 952A      DEC	R18
    02B7 F7B9      BNE	0x02AF
    02B8 F40E      BRTC	0x02BA
    02B9 2D0E      MOV	R16,R14
    02BA 90E9      LD	R14,Y+
    02BB 90F9      LD	R15,Y+
    02BC 9129      LD	R18,Y+
    02BD 9508      RET
pop_gset2:
    02BE E0E2      LDI	R30,2
    02BF C00E      RJMP	pop
pop_gset3:
    02C0 E0E4      LDI	R30,4
    02C1 C00C      RJMP	pop
push_gset5:
    02C2 92FA      ST	R15,-Y
    02C3 92EA      ST	R14,-Y
push_gset4:
    02C4 92DA      ST	R13,-Y
    02C5 92CA      ST	R12,-Y
push_gset3:
    02C6 92BA      ST	R11,-Y
    02C7 92AA      ST	R10,-Y
push_gset2:
    02C8 937A      ST	R23,-Y
    02C9 936A      ST	R22,-Y
push_gset1:
    02CA 935A      ST	R21,-Y
    02CB 934A      ST	R20,-Y
    02CC 9508      RET
pop_gset1:
    02CD E0E1      LDI	R30,1
pop:
    02CE 9149      LD	R20,Y+
    02CF 9159      LD	R21,Y+
    02D0 FDE0      SBRC	R30,0
    02D1 9508      RET
    02D2 9169      LD	R22,Y+
    02D3 9179      LD	R23,Y+
    02D4 FDE1      SBRC	R30,1
    02D5 9508      RET
    02D6 90A9      LD	R10,Y+
    02D7 90B9      LD	R11,Y+
    02D8 FDE2      SBRC	R30,2
    02D9 9508      RET
    02DA 90C9      LD	R12,Y+
    02DB 90D9      LD	R13,Y+
    02DC FDE3      SBRC	R30,3
    02DD 9508      RET
    02DE 90E9      LD	R14,Y+
    02DF 90F9      LD	R15,Y+
    02E0 9508      RET
lsl8:
    02E1 2311      TST	R17
    02E2 F019      BEQ	0x02E6
    02E3 0F00      LSL	R16
    02E4 951A      DEC	R17
    02E5 CFFB      RJMP	lsl8
    02E6 9508      RET
mpy16s:
    02E7 920A      ST	R0,-Y
    02E8 921A      ST	R1,-Y
    02E9 2400      CLR	R0
    02EA 2411      CLR	R1
    02EB 3000      CPI	R16,0
    02EC 0701      CPC	R16,R17
    02ED F041      BEQ	0x02F6
    02EE 9516      LSR	R17
    02EF 9507      ROR	R16
    02F0 F410      BCC	0x02F3
    02F1 0E02      ADD	R0,R18
    02F2 1E13      ADC	R1,R19
    02F3 0F22      LSL	R18
    02F4 1F33      ROL	R19
    02F5 CFF5      RJMP	0x02EB
    02F6 2D00      MOV	R16,R0
    02F7 2D11      MOV	R17,R1
    02F8 9019      LD	R1,Y+
    02F9 9009      LD	R0,Y+
    02FA 9508      RET

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