cpu_intf.vhd

cpu的VHDL的源代码

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--
-- Title       : cpu_intf
-- Design      : demo2
-- Author      : suli
-- Company     : Tsinghua
--
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--
-- File        : cpu_intf.vhd
-- Generated   : Wed Oct 30 08:42:43 2002
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {cpu_intf} architecture {cpu_intf}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity cpu_intf is
	 port(
		mbeb			: in std_logic;
	
		ale  			: in std_logic;
		csb  			: in std_logic;
		wr_rwb 			: in std_logic;
		rd_eb 			: in std_logic;
		a    			: in std_logic_vector(5 downto 0);
		d    			: inout std_logic_vector(7 downto 0);

		rd             	: out  std_logic;
		wr             	: out  std_logic;
		add          	: out  std_logic_vector(5 downto 0);
		mbd_in         	: out  std_logic_vector(7 downto 0);
		mbd_out        	: in std_logic_vector(7 downto 0);
		intbuf         	: in std_logic		
		);
end cpu_intf;					  

--		mbeb 			: in std_logic;
-- when mbeb = '1' , intel mode; when mbeb = '0' , motorola mode;

--		wr_rwb 			: in std_logic;
-- when intel mode,    wr_rwb ----> wr (low active)
-- when motorola mode, wr_rwb ----> ='0' , write operation; = '1', read operation..

--		rd_eb 			: in std_logic;
-- when intel mode, rd_eb ----> rd (low active)
-- when motorola mode, rd_eb ----> ='1', enable;

architecture cpu_intf of cpu_intf is
--address
signal ain    : std_logic_vector(5 downto 0);

--operation
signal intelwr , intelrd : std_logic;
signal motorwr , motorrd : std_logic;
signal wr_enab , rd_enab : std_logic; --low active
--signal mbd_in: std_logic_vector(7 downto 0);
--data
signal dout_enab   : std_logic;		  --low active

begin																			
	
--******************************************************************************	
--		add            	: out  std_logic_vector(11 downto 0);
--******************************************************************************
process(ale, a(5 downto 0))
begin		
	if ale = '1' then
		ain <= a(5 downto 0);
	end if;	
end process;	

--add12(11 downto 8) <= a(11 downto 8);
add(5 downto 0)  <= ain;
	
--******************************************************************************
-- rd || wr operation......
--******************************************************************************
--signal wr_rwb : std_logic;
--signal rd_eb  : std_logic;	
--mbeb 			: in std_logic;
--signal intelwr , intelrd : std_logic;
--signal motorwr , motorrd : std_logic;
--signal wr_enab , rd_enab : std_logic;	  
intelwr <= '0' when mbeb = '1' and wr_rwb = '0' and rd_eb = '1' else '1';
intelrd <= '0' when mbeb = '1' and wr_rwb = '1' and rd_eb = '0' else '1';	

motorwr <= '0' when mbeb = '0' and wr_rwb = '0' and rd_eb = '1' else '1';
motorrd <= '0' when mbeb = '0' and wr_rwb = '1' and rd_eb = '1' else '1';
	
wr_enab <= '0' when intelwr = '0' or motorwr = '0' else '1';
rd_enab <= '0' when intelrd = '0' or motorrd = '0' else '1';
	
--		wr             	: out  std_logic;	
--		rd             	: out  std_logic;
wr <= wr_enab;
rd <= rd_enab;

--******************************************************************************
--		mbd_in         	: out  std_logic_vector(7 downto 0);
--		mbd_out        	: in std_logic_vector(7 downto 0);	
--		d    			: inout std_logic_vector(7 downto 0);
--******************************************************************************
--signal dout_enab   : std_logic;												
dout_enab <= '0' when csb = '0' and rd_enab = '0' else '1';

d         <= mbd_out when dout_enab = '0' else (others => 'Z');
mbd_in    <= d;	

--mbd_in_1 <= mbd_in(7) or mbd_in(6) or mbd_in(5) or mbd_in(4) or mbd_in(3) or mbd_in(2) or mbd_in(1) or mbd_in(0);

	
end cpu_intf;