adcdac.asm

this a DSP program for sine wave design

	.title	  "TMS320F206EVM Sampling Routin[AD876] and DAC routine[THS5651]"
    .global		_c_int0  
************************************************
**  Input signal:0-2Vp-p
************************************************
*===============================================================
*  TMS320F206EVM resources list
*------------------------------------
*
*    program: 
*			  On chip flash:(0000-7fffh), Hard Jump Close
*			  EXT-SRAM:(0000h-7fffh), Hard Jump Open
*             On chip DARAM: B0(FF00-FFFFh, by CNF=1)
*			  On chip SARAM:(8000h-8fffh)(share with data, by PON-->1)
*
*    data(local):
*			  On chip DARAM: B0(200-2FFh, by CNF=0), B1(300-3FFh), B2(60-7Fh)
*			  Onchip SARAM(800-17ffh) (share with program, by DON-->1)
*			  EXT-SRAM:(800-17ffh, by DON-->0), (1800-7fffh)
*			  EXT-SRAM-read(8000h-0BFFFh): A/D
*			  EXT-SRAM-Write(8000h-0BFFFh): D/A     
*
*    Data(Global): 
*			  EXT-BUS: 8000h-0ffffh
*    I/O: 
*			  On chip resources
*			  EXT-BUS: 8000h-0ffffh   
*
*===============================================================
DLOGLWS	.macro  waitST
* 	waitST=0 -->0 wait state, waitST=449h -->IO:2/D:1/PU:1/PD:1 wait state
	lacl	#0	    ;00h local: 0-FFFFh, 64KWs
                    ;080h local: 0-7FFFh, 32KWs, global:8000h-0ffffh,32KWs
	ldp		#0h  	; set DP=0
	sacl	GREG	; local: 0-7FFFh, 32KWs
					; global: 8000h-FFFFh, 32KWs
	splk	#waitST,60h	;
	out		60h,WSGR	; set wait states
	.endm
*
*================================================================
*  program: EXT-SRAM(0000-7fffh, no wait state); SARAM(8000h-8fffh)(share with data)
*  data: local =B0(200-2FFh), B1(300-3FFh), B2(60-7Fh)
*		   EXT-SRAM: 1800h-7fffh, no wait state
*		   SARAM(800-17ffh) (share with program)
*		   EXT-SRAM-Write(8000h-0BFFFh): D/A     
*===============================================================
; init sampling
;===============
IO0WORK	.set	1h		; output IO0 is high, D F/F Working
IO0CLR	.set	0h		; output IO0 is low, ready to start
*
	.include	"DSP_INIT.H"	; Variable and register declaration
	.include	"DSP_VECT.H"	; Vector label declaration
	.text
*     
_c_int0:
start:			; program begin here
*				; first initialize DSP's working status
	setc	INTM		; Disable all interrupt
	clrc	CNF		; B0 is used as data ram 200h
	ldp		#0
	lacl	#111b
	sacl	60h
	out		60h,PMST 	; set sram to data & program,
						; and set microProcessor mode(use EXT SRAM)
*
	spm 	0	 	; PM=00,no shift of PREG output
	clrc	SXM		; suppresses sign-extension
;*	setc	OVM		; overflow: most positive or negative
	clrc	OVM		; overflow: normal
	clrc	XF		; set XF=0 
*
	ldp		#0
	splk	#0ffffh, IFR	; clear interrupts
*	splk	#0002h, IMR		; enable INT2/3 interrupt, mask the others
	splk	#0000h, IMR		; mask all interrupts
	splk	#11h, 60h		; infact, INT3 is not used and INT2 is used for
	out		60h, ICR     	; the internal trigger and  the external trigger
							; INT2 is default
	call	timset		    ; setting timer initialization (2Mz/0.5us)
						    ; sampling ratio(1MSPS)
	splk	#0e001h, 60h    ; configure bit IO3..1 as input and IO0 as Output
	out		60h, ASPCR		; setting
	splk	#0000h,	60h       			
	out		60h, IOSR
	splk	#0001h,	60h       			
	out		60h, IOSR
*
	DLOGLWS 449h			; setting sampling Greg and WSreg
    mar		*, ar0
	lar		ar0, #1
wait1ms:
	rpt		#0fh
	nop      
	banz	wait1ms, *+ 
*============================================         
;  sampling begin
*
    mar		*, ar0
	lar		ar0, #200h
	lar		ar1, #05fffh;2000h
	sar		ar1, *, ar1
goonsam1
	lar		ar1, #2000h
	lar		ar2, #4000h	
    ldp		#(8000h>>7)
goonsam:            ; sigma=26T-->0.833MHz(1.2uS)
	lacc		00  ;, 6   ; 8000h=A/D, 2T+1T+1T=4T   
	sub		#200h	; 4T   ;;;;;;;;// the 1st board not need
	sacl	00	    ; to DAC, 2T_+2T+1T+1T=6T
;	nop		;1T+1T=2T
;	nop		;1T+1T=2T
;	nop		;1T+1T=2T
;	nop		;1T+1T=2T
	sacl	*+, ar2	; *=ar1/save d(n) to SRAM, 2T+1T+1T=4T
	banz	goonsam, *-, ar1 ; *=ar2/counter, 4T+4T=8T

;	rpt		*
;	bldd		00h, #2000h	;, ar2      (6 n +4) T
	b		goonsam1	; *=ar3/counter, 4T
	b   	goonsam1	; *=ar3/counter, 4T
*========================================		
    b	$
*=====================================
*	.title	"Radar Echo Data sampling clock generation"
*	file: DSP_CLK.asm
*************************************************************************
* WRDPS USING DSP: RADAR ECHO DATA PROCESSOR, 
*                            SAMPLING clock generator PROGRAM
* AUTHER: MR. YAOZHENDONG, OCT,23,1998
*************************************************************************
*  clkout1 = 50 nS, TDDR <--- 0, PRD <--- 9, then f=20Mhz/[(0+1)*(12+1)]=1.5384Mhz
*  T = 1/1.5384Mhz = 0.65uS, so the A/D CLK is 1.5384/2=769231Hz, Tclk=1.3uS
*************************************************************************
* 		TCR: IS&FFF9h
*	      +-----------+------+------+-----+-----+-----+------+
*	      |	15 ... 12 |  11  |  10  | 9 6 |  5  |  4  | 3  0 |
*	      +-----------+------+------+-----+-----+-----+------+
*	      |	 Reserve  | FREE | SOFT | PSC | TRB | TSS | TDDR |
*	      +-----------+------+------+-----+-----+-----+------+
*========================================================
timset:            		; initialize the timer
	lar		ar1,#300h      	; T = 0.65 uS
	mar		*,ar1
	splk	#12,*
	out		*,PRD		; set PRD = 12
	splk	#0,*
	out		*,TIM		; set TIM=00000
	splk	#0c20h,*	; PSC,TDDR are zero, reload, restat
	out		*,TCR
	ret
*-------------------------------
*
inpt23: 			; trigger coming, generating INT2,
				    ; start sampling and filtering
	lar		ar7,#00h
	clrc	INTM
	ret
*==================================
inpt1:	ret 			;Unused interrupt
codtx:	ret
codrx:	ret
uart:	ret
timer:	ret
y5nmi:  ret
*=====================================
		.end