s3c2410_sm501.c

s3c2410 sm501 在SMDK开发包的可运行源代码

/*
*  linux/drivers/video/sm501.c
*
*
*   Based on pxafb.c Copyright (C) Eric A. Thomas
*   Based on sa1100fb.c Copyright (C) Eric A. Thomas
*   Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License.  See the file COPYING in the main directory of this archive for
* more details.
*
*	        Silicon Motion SM501 Frame Buffer Driver
*/

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/cpufreq.h>
#include <linux/sysctl.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/uaccess.h>
#include <linux/delay.h>


#include <video/fbcon.h>
#include <video/fbcon-mfb.h>
#include <video/fbcon-cfb8.h>
#include <video/fbcon-cfb16.h>
#include <video/fbcon-cfb32.h>

#define arraysize(x)	(sizeof(x)/sizeof(*(x)))

#define VGA_640X480 1

/*
* debugging?
*/
#undef DEBUG
/*
* Complain if VAR is out of range.
*/
#define DEBUG_VAR 2

#include "sm501.h"

char *sm501Reg;
static char *sm501Mem;

typedef struct _mode_table_t
{
	// Horizontal timing.
	int			horizontal_total;
	int			horizontal_display_end;
	int			horizontal_sync_start;
	int			horizontal_sync_width;
	polarity_t	horizontal_sync_polarity;

	// Vertical timing.
	int 		vertical_total;
	int 		vertical_display_end;
	int 		vertical_sync_start;
	int 		vertical_sync_height;
	polarity_t	vertical_sync_polarity;

	// Refresh timing.
	long		pixel_clock;
	long		horizontal_frequency;
	long		vertical_frequency;
} mode_table_t, *pmode_table_t;




// Clock value structure.
typedef struct clock_select_t           //hqj_add_function start
{
	long	mclk;
	int		divider;
	int		shift;
} clock_select_t, *pclock_select_t;

typedef struct _reg_table_t
{
	unsigned long	clock;
	unsigned long	control;
	unsigned long	fb_width;
	unsigned long	horizontal_total;
	unsigned long	horizontal_sync;
	unsigned long	vertical_total;
	unsigned long	vertical_sync;
	unsigned long	width;
	unsigned long	height;
	display_t		display;
} reg_table_t, *preg_table_t;

//int sm501mode = 10;      //hqj   1024*768
int sm501mode = 6;      //hqj   800*600     //hqj_06_12_20
int sm501bpp = 16;
int	sm501out = 1;        //hqj


static int error;

typedef enum _panel_state_t
{
	PANEL_OFF,
	PANEL_ON,
}
panel_state_t;
mode_table_t mode_table[] =
{
	/*----------------------------------------------------------------------------------------
	* H.	H.    H.     H.   H.        V.   V.    V.    V.   V.        Pixel     H.     V.
	* tot.	disp. sync   sync sync      tot. disp. sync  sync sinc      clock     freq.  freq.
	*      end   start  wdth polarity       end   start hght polarity
	*---------------------------------------------------------------------------------------*/

	/* 640 x 480 */
	{  800, 640,  656,   96,  NEGATIVE, 525, 480,  490,  2,   NEGATIVE, 25175000, 31469, 60 },
	{  832, 640,  664,   40,  NEGATIVE, 520, 480,  489,  3,   NEGATIVE, 31500000, 37861, 72 },
	{  840, 640,  656,   64,  NEGATIVE, 500, 480,  481,  3,   NEGATIVE, 31500000, 37500, 75 },
	{  832, 640,  696,   56,  NEGATIVE, 509, 480,  481,  3,   NEGATIVE, 36000000, 43269, 85 },

	/* 800 x 600 */
	{ 1024, 800,  824,   72,  POSITIVE, 625, 600,  601,  2,   POSITIVE, 36000000, 35156, 56 },
	{ 1056, 800,  840,  128,  POSITIVE, 628, 600,  601,  4,   POSITIVE, 40000000, 37879, 60 },
	{ 1040, 800,  856,  120,  POSITIVE, 666, 600,  637,  6,   POSITIVE, 50000000, 48077, 72 },
	{ 1056, 800,  816,   80,  POSITIVE, 625, 600,  601,  3,   POSITIVE, 49500000, 46875, 75 },
	{ 1048, 800,  832,   64,  POSITIVE, 631, 600,  601,  3,   POSITIVE, 56250000, 53674, 85 },

	/* 1024 x 768*/
	{ 1344, 1024, 1048, 136,  NEGATIVE, 806, 768,  771,  6,   NEGATIVE, 65000000, 48363, 60 },
	{ 1328, 1024, 1048, 136,  NEGATIVE, 806, 768,  771,  6,   NEGATIVE, 75000000, 56476, 70 },
	{ 1312, 1024, 1040,  96,  POSITIVE, 800, 768,  769,  3,   POSITIVE, 78750000, 60023, 75 },
	{ 1376, 1024, 1072,  96,  POSITIVE, 808, 768,  769,  3,   POSITIVE, 94500000, 68677, 85 },

	/* End of table. */
	{ 0, 0, 0, 0, NEGATIVE, 0, 0, 0, 0, NEGATIVE, 0, 0, 0 },
};
//hqj_add_function end
// Perform a rounded division.
long roundDiv(long num, long denom)
{
	/* n / d + 1 / 2 = (2n + d) / 2d */
	return (2 * num + denom) / (2 * denom);
}


// Finds clock closest to the requested.
long findClock(long requested_clock, clock_select_t *clock, display_t display)     //hqj_add_function
{
	long	mclk;
	int		divider, shift;
	long	best_diff = 999999999;

	// Try 288MHz and 336MHz clocks.
	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000)
	{
		// For CRT, try dividers 1 and 3, for panel, try divider 5 as well.
		for (divider = 1; divider <= (display == PANEL ? 5 : 3);
			divider += 2)
		{
			// Try all 8 shift values.
			for (shift = 0; shift < 8; shift++)
			{
				// Calculate difference with requested clock.
				long diff = roundDiv(mclk, divider << shift) - requested_clock;
				if (diff < 0)
				{
					diff = -diff;
				}

				// If the difference is less than the current, use it.
				if (diff < best_diff)
				{
					// Store best difference.
					best_diff = diff;

					// Store clock values.
					clock->mclk = mclk;
					clock->divider = divider;
					clock->shift = shift;
				}
			}
		}
	}

	printk("clock->mclk=%d, clock->divider=%d,clock->shift=%d\n",clock->mclk,clock->divider,clock->shift);

	//clock->shift = 1;
	//clock->divider = 3;
	// printk("force shift=1,divider=2\n");
	// Return best clock.
	return clock->mclk / (clock->divider << clock->shift);
}

// Fill the register structure.
void setModeRegisters(reg_table_t *register_table, mode_table_t *mode, display_t display, int bpp)   //hqj_add_function
{
	clock_select_t clock;
	memset(&clock, 0, sizeof(clock));
	//printk(" setModeRegisters\n");
	// Calculate the clock register values.
	findClock(mode->pixel_clock * 2, &clock, display);

	if (display == PANEL)
	{
		// Set clock value for panel.

		register_table->clock
			= (clock.mclk == 288000000
			? FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 288)
			: FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 336))
			| (clock.divider == 1
			? FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 1)
			: (clock.divider == 3
			? FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 3)
			: FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 5)))
			| FIELD_VALUE(0, CURRENT_POWER_CLOCK, P2XCLK_SHIFT, clock.shift);
		//printk("setModeRegisters ::CURRENT_POWER_CLOCK=%x\n",regRead32(CURRENT_POWER_CLOCK));
		//printk("register_table->clock=%d\n",register_table->clock);
		// Set control register value.
		register_table->control
			= (mode->vertical_sync_polarity == POSITIVE
			? FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH)
			: FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW))
			| (mode->horizontal_sync_polarity == POSITIVE
			? FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH)
			: FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW))
			| FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)
			| FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE)
			| (bpp == 8
			? FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 8)
			: (bpp == 16
			? FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 16)
			: FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 32)));

		// Set timing registers.
		register_table->horizontal_total
			= FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL,
			mode->horizontal_total - 1)
			| FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END,
			mode->horizontal_display_end - 1);

		register_table->horizontal_sync
			= FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH,
			mode->horizontal_sync_width)
			| FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START,
			mode->horizontal_sync_start - 1);

		register_table->vertical_total
			= FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL,
			mode->vertical_total - 1)
			| FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END,
			mode->vertical_display_end - 1);

		register_table->vertical_sync
			= FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT,
			mode->vertical_sync_height)
			| FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START,
			mode->vertical_sync_start - 1);
	}
	else
	{
		// Set clock value for CRT.
		register_table->clock
			= (clock.mclk == 288000000
			? FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 288)
			: FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 336))
			| (clock.divider == 1
			? FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 1)
			: FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 3))
			| FIELD_VALUE(0, CURRENT_POWER_CLOCK, V2XCLK_SHIFT, clock.shift);

		// Set control register value.
		register_table->control
			= (mode->vertical_sync_polarity == POSITIVE
			? FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH)
			: FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW))
			| (mode->horizontal_sync_polarity == POSITIVE
			? FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH)
			: FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW))
			| FIELD_SET(0, CRT_DISPLAY_CTRL, SELECT, CRT)
			| FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE)
			| FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE)
			| (bpp == 8
			? FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 8)
			: (bpp == 16
			? FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 16)
			: FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 32)));

		// Set timing registers.
		register_table->horizontal_total
			= FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL,
			mode->horizontal_total - 1)
			| FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END,
			mode->horizontal_display_end - 1);

		register_table->horizontal_sync
			= FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH,
			mode->horizontal_sync_width)
			| FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START,
			mode->horizontal_sync_start - 1);

		register_table->vertical_total
			= FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL,
			mode->vertical_total - 1)
			| FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END,
			mode->vertical_display_end - 1);
		register_table->vertical_sync
			= FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT,
			mode->vertical_sync_height)
			| FIELD_VALUE(0, CRT_VERTICAL_SYNC, START,
			mode->vertical_sync_start - 1);
	}

	// Calculate frame buffer width and height.
	register_table->fb_width = mode->horizontal_display_end * (bpp / 8);
	register_table->width = mode->horizontal_display_end;
	register_table->height = mode->vertical_display_end;

	// Save display type.
	register_table->display = display;
}



mode_table_t *findMode(mode_table_t *mode_table, int width, int height, long refresh_rate)
{ //printk("w=%d,h=%d,r=%d\n",width, height, refresh_rate);
	// Walk the entire mode table.
	while (mode_table->pixel_clock != 0)
	{  //printk("mode_table_t w=%d,h=%d,r=%d\n",mode_table->horizontal_display_end, mode_table->vertical_display_end, mode_table->vertical_frequency);

		// If this mode matches the requested mode, return it!
		if ((mode_table->horizontal_display_end == width)
			&& (mode_table->vertical_display_end == height)
			&& (mode_table->vertical_frequency == refresh_rate))
		{
			//printk("mode_table_t w=%d,h=%d,r=%d\n",mode_table->horizontal_display_end, mode_table->vertical_display_end, mode_table->vertical_frequency);
			return(mode_table);
		}

		// Next entry in the mode table.
		mode_table++;
	}

	// No mode found.
	return(NULL);
}

// Converts the VESA timing into Voyager timing.
void adjustMode(mode_table_t *vesaMode, mode_table_t *mode, display_t display)
{
	long blank_width, sync_start, sync_width;
	clock_select_t clock;
	//printk("adjustMode\n");
	// Calculate the VESA line and screen frequencies.
	vesaMode->horizontal_frequency = roundDiv(vesaMode->pixel_clock, vesaMode->horizontal_total);
	vesaMode->vertical_frequency = roundDiv(vesaMode->horizontal_frequency, vesaMode->vertical_total);

	// Calculate the sync percentages of the VESA mode.
	blank_width = vesaMode->horizontal_total - vesaMode->horizontal_display_end;
	sync_start = roundDiv((vesaMode->horizontal_sync_start - vesaMode->horizontal_display_end) * 100, blank_width);
	sync_width = roundDiv(vesaMode->horizontal_sync_width * 100, blank_width);

	// Copy VESA mode into Voyager mode.
	*mode = *vesaMode;

	// Find the best pixel clock.
	mode->pixel_clock = findClock(vesaMode->pixel_clock * 2, &clock, display) / 2;

	// Calculate the horizontal total based on the pixel clock and VESA line
	// frequency.
	mode->horizontal_total = roundDiv(mode->pixel_clock, vesaMode->horizontal_frequency);

	// Calculate the sync start and width based on the VESA percentages.
	blank_width = mode->horizontal_total - mode->horizontal_display_end;
	mode->horizontal_sync_start = mode->horizontal_display_end + roundDiv(blank_width * sync_start, 100);
	mode->horizontal_sync_width = roundDiv(blank_width * sync_width, 100);

	// Calculate the line and screen frequencies.
	mode->horizontal_frequency = roundDiv(mode->pixel_clock, mode->horizontal_total);
	mode->vertical_frequency = roundDiv(mode->horizontal_frequency, mode->vertical_total);
	//printk("horizontal_total=%d\n",mode->horizontal_total);
	//printk("horizontal_display_end=%d\n",mode->horizontal_display_end);
	//printk("horizontal_sync_start=%d\n",mode->horizontal_sync_start);
	//printk("horizontal_sync_width=%d\n",mode->horizontal_sync_width);
	//printk("vertical_total=%d\n",mode->vertical_total);
	//printk("vertical_display_end=%d\n",mode->vertical_display_end);
	//printk("vertical_sync_start=%d\n",mode->vertical_sync_start);
	//printk("vertical_sync_height=%d\n",mode->vertical_sync_height);
	//printk("pixel_clock=%d\n",mode->pixel_clock);
	//printk("horizontal_frequency=%d\n",mode->horizontal_frequency);
	//printk("vertical_frequency=%d\n",mode->vertical_frequency);
}


u_long regRead32(u_long nOffset)
{
#if DEBUG > 1
	u_long ret = *(volatile unsigned long *)(sm501Reg+nOffset);
	if (DEBUG)
		printk("%s: %#lx --> %#lx\n", __FUNCTION__, nOffset, ret);
	return ret;
#else
	return *(volatile unsigned long *)(sm501Reg+nOffset);
#endif
}

void regWrite32(u_long nOffset, u_long nData)
{

	u_long readback;
	//if (nOffset < 0x00080800)
	//printk("nOffset < 0x00080800 %s: %#lx <-- %#lx\n", __FUNCTION__, nOffset, nData);

	*(volatile unsigned long *)(sm501Reg+nOffset) = nData;

	readback = *(volatile unsigned long *)(sm501Reg+nOffset);
	if (readback != nData)
		printk("Warning: offset=%#lx  writedata=%#lx <-- readout=%#lx\n",nOffset, nData, readback);

}
void memWrite32(u_long nOffset, u_long nData)
{
#if DEBUG > 1
	u_long readback;

	//printk("%s: %#lx <-- %#lx\n", __FUNCTION__, nOffset, nData);

	*(volatile unsigned long *)(sm501Mem+nOffset) = nData;

	readback = *(volatile unsigned long *)(sm501Mem+nOffset);
	if (readback != nData)
		printk("Warning: %#lx\n", readback);
#else
	*(volatile unsigned long *)(sm501Mem+nOffset) = nData;
	//printk("%s: %#lx <-- %#lx\n", __FUNCTION__, nOffset, nData);

#endif
}



static int __init sm501_detect(void)
{


	int sm501_device_id =0;