config.c

基于跳频的音频连接系统设计（Mono Audio Link Using Frequency Hopping）及源代码

	
	ADC0LTH = 0x00;	// ADC Less-Than High Byte Register
	ADC0LTL = 0x00;	// ADC Less-Than Low Byte Register
	ADC0GTH = 0xFF;	// ADC Greater-Than High Byte Register
	ADC0GTL = 0xFF;	// ADC Greater-Than Low Byte Register

 /***************************************** Timer Configuration ****************************************/

	CKCON =   0x00;	// Clock Control Register
	TH0 = 	  0x00;	// Timer 0 High Byte
	TL0 = 	  0x00;	// Timer 0 Low Byte
	TH1 = 	  0x00;	// Timer 1 High Byte
	TL1 = 	  0x00;	// Timer 1 Low Byte
	TMOD = 	  0x00;	// Timer Mode Register
	TCON =    0x05;	// Timer Control Register (Ext. int 0/1 are edge triggered)

	RCAP2H =  FH_TIMER_AUTORELOAD_H;	// Timer 2 Capture Register High Byte
	RCAP2L =  FH_TIMER_AUTORELOAD_L;	// Timer 2 Capture Register Low Byte	
	TH2 =     FH_TIMER_AUTORELOAD_H;	// Timer 2 High Byte	
	TL2 =     FH_TIMER_AUTORELOAD_L;	// Timer 2 Low Byte	
    T2CON =   0x00;	// Timer 2 Control Register	

	TMR3H =   0x00;	// Timer 3 High Byte
	TMR3L =   0x00;	// Timer 3 Low Byte
    TMR3CN =  0x00;	// Timer 3 Control Register

	TMR3CN &= 0xFD;									// Timer 3 running on SYSCLK/12
	if (!M_MASTER) {								// Set start/auto-reload value
		TMR3RLL = ACK_TIMER_AUTORELOAD_L;	
		TMR3RLH = ACK_TIMER_AUTORELOAD_H;									
	} else {
		TMR3RLL = CLEAR_AHEAD_TIMER_AUTORELOAD_L;	
		TMR3RLH = CLEAR_AHEAD_TIMER_AUTORELOAD_H;
	}

 /***************************************** Reset Source Configuration *********************************/

// Bit 7  | Bit 6  | Bit 5  | Bit 4  | Bit 3 | Bit 2 | Bit 1 | Bit 0
//------------------------------------------------------------------     
//    R	 |   R/W  |  R/W   |  R/W   |   R   |   R   |  R/W  |  R
//------------------------------------------------------------------
//  JTAG  |Convert | Comp.0 | S/W    | WDT   | Miss. | POR   | HW
// Reset  |Start   | Reset/ | Reset  | Reset | Clock | Force | Pin
// Flag   |Reset/  | Enable | Force  | Flag  | Detect| &     | Reset
//        |Enable  | Flag   | &      |       | Flag  | Flag  | Flag
//        |Flag    |        | Flag   |       |       |       |
//------------------------------------------------------------------
// NOTE! : Comparator 0 must be enabled before it is enabled as a 
// reset source.
//
// NOTE! : External CNVSTR must be enalbed through the crossbar, and
// the crossbar enabled prior to enabling CNVSTR as a reset source 
//------------------------------------------------------------------

	RSTSRC = 0x00;	// Reset Source Register


 /***************************************** Interrupt Configuration ************************************/


	IE = 0x01;		    //Interrupt Enable (INT0 enabled, INT1 disabled)
	IP = 0x00;		    //Interrupt Priority
	EIE1 = 0x00;		//Extended Interrupt Enable 1
	EIE2 = 0x00;		//Extended Interrupt Enable 2
	EIP1 = 0x00;		//Extended Interrupt Priority 1
	EIP2 = 0x00;		//Extended Interrupt Priority 2
} 



 /*******************************************************************************************************
 * 											System setup    				                			*
 *******************************************************************************************************/

void smCodecWriteReg(BYTE regAddr, WORD regData) {
	STA = 1; SI = 0; while(!SI);// Send start condition
	SMB0DAT = 0x36;				// Send slave address + WR bit
	STA = 0; SI = 0; while(!SI);
	SMB0DAT = (regAddr<<1)|(regData>>8); // Send data byte with register address and MSB of data
	SI = 0; while(!SI);
	SMB0DAT = regData&0xFF; 	// Send data byte with 8 LSB of data
	SI = 0; while(!SI);
	STO = 1; SI = 0; 			// Send stop condition
}


//Configure the TLV320 codec via the SMBus
void codecInit (void) {

	smCodecWriteReg(15,0x000);	// Reset device	
	smCodecWriteReg(0, 0x118);	// Left line input channel volume/mute reg
	smCodecWriteReg(1, 0x118);	// Right line input channel volume/mute reg
	smCodecWriteReg(2, 0x170);	// Left headphone volume reg
	smCodecWriteReg(3, 0x170);	// Right headphone volume reg
	smCodecWriteReg(7, 0x002);	// Digital audio interface format (12S format)
	smCodecWriteReg(8, 0x020);	// Sample rate control reg (44.1 kHz DAC/ADC)
	smCodecWriteReg(9, 0x001);	// Digital interface activation reg

	if (!M_MASTER) {
		// Device is radio master - jumber 1/3 (audio in)
		if (!IN_SEL) {
			smCodecWriteReg(4, 0x005);	// Analog audio path reg (Line in, DAC off)
		} else {
			smCodecWriteReg(4, 0x002);	// Analog audio path reg (Mic in, DAC off)	
		}
		smCodecWriteReg(5, 0x005);	// Digital audio path reg (DACM=0, DEEMP=Disabled, ADCHP=0)
		smCodecWriteReg(6, 0x038);	// Power down control (OSc, DAC and outputs off)
	} else {
		// Device is radio slave - no jumper 1/3 (audio out)
		smCodecWriteReg(4, 0x012);	// Analog audio path reg (Line in)
		smCodecWriteReg(5, 0x000);	// Digital audio path reg (DACM=0, DEEMP=Disabled, ADCHP=0)
		smCodecWriteReg(6, 0x023);	// Power down control (OSc, ADC, MIC and line in off)
	}
}


// Configure busses (P2 and SPI) for radio/master slave
void busSetup() {

	// SPI settings
	SPI0CN |= 0x01;		// Set the enable SPI flag
	SPI0CN |= 0x02;		// Set enable master mode flag
	SPI0CFG |= 0x07;	// Set frame size to 8bit
	SPI0CKR  = 0x00; 	// Set SPI clock rate to 11,2MHz (max)

	if (!M_MASTER) {	// Device is radio master - jumber 1/3 (audio in)		
	 	PRT2CF = 0x00;	// Set A_PDATA to high impedance
		A_PDATA = 0xFF;	// A_PDATA (P2) is input
		A_OE4094 = 1;	// 4094 drives bus
	} else {			// Device is radio slave - no jumper 1/3 (audio out)			
		A_OE4094 = 0;	// Set 4094 to high impedance
		PRT2CF = 0xFF;	// A_PDATA (P2) is output
	}
}


// Sunchronize with R/L control (A_LRCK and A_BCLK16)
void syncRLInt() {
	while((A_LRCK && A_BCLK16));
	while(!(A_LRCK && A_BCLK16));	// Wait for the condition preceding L_MSB
	wait(1);						// Wait a few cycles so we don't catch the frist 
									// interrupt for R_LSB
	ENABLE_GLOBAL_INT();
}


void rfSetup(void) {

	RF_SETTINGS rfs = {

		// Generated by SmartRF Studio
		0x0000,		//	FSCTRL  Frequency synthesiser main control and status  
		0x0965,		//	FSDIV   Frequency synthesiser frequency division control
		0x0040,  	//	MDMCTRL Modem main control and status
		0x000F,		//	FREND   Analog Front-End Control
		0x0000,		//	RSSI    information
    	0x16B0,		//	IOCFG   I/O configuration register (No CRC_OK (GIO6): 0x7EB0, With CRC_OK: 0x16B0)
    	0x0000,		//  MSMTC   Finite State Machine time constants
		0x7FFF,		//	MANAND  Manual signal AND-override register 
		0x0000,		//	PAMTST  PA and transmit mixers test register
		0x0000,		//	LMTST   LNA and receive mixers test register
		0x034B,  	//	MDMTST0 Modem test register 0
		0x004B,   	//	MDMTST1 Modem test register 1
		0x0000,		//	DACTST  DAC Test register
		0x0000,		//	FSTST0  Test register: VCO array results and override
		0x0000,		//	FSTST1  Test register: VC DAC manual control VCO current constant
    	0x0DF0,		//	GRMDM   Generic radio modem control
    	0x0000,		//	GRDEC   Generic radio decimation control and status
		0x0010		//  INT		Interrupt control
	};

	// IOCFG   I/O configuration register for master device
	// No CRC_OK (GIO6): 0x7EB0, With CRC_OK: 0x16B0
	if (!M_MASTER) {
		rfs.IOCFG = 0x7EB0;
	} 

	rfInit(&rfs, TRUE);	
	rfOn();
}

void sysConfig(void) {

	DISABLE_GLOBAL_INT();	// Enabled again by syncRLInt()

	// RF default state
	R_RX = 0;		
	R_TX = 0;

	// Leds
	if (!M_MASTER) {
		M_BLED = 0;
		M_GLED = 1;
	} else {
		M_BLED = 1;
		M_GLED = 0;
	}

	// Reset SP-DIF to I2S chip
	S_RST = 0;
	if (!M_MASTER) {
		wait(5);
		S_RST = 1;
	}
	
	setISRvector();			// Set the the ISR vector address for INT0 (master/slave)
	busSetup();		
	codecInit ();
	clearMem();				// Set all addresses in XDATA to 0x00 (for debugging)
	rfSetup();
	setRegs();				// Set default buffer offset/base addresses
	if (!M_MASTER) {
		syncRLInt();
	}
}


// Busy wait loop
void wait(UINT16 c) {
	UINT16 n;
	for(n = 0; n < c; n++);
}

 /*******************************************************************************************************/