fifo.asm

基于跳频的音频连接系统设计（Mono Audio Link Using Frequency Hopping）及源代码

;*******************************************************************************************************
;*                                                                                                     *
;*        **********                                                                                   *
;*       ************                                                                                  *
;*      ***        ***                                                                                 *
;*      ***   +++   ***                                                                                *
;*      ***   + +   ***                                                                                *
;*      ***   +            			            				     FIFO I/O module															 *			
;*      ***   + +   ***      														 								                               *
;*      ***   +++   ***                                                                                *
;*      ***        ***                                                                                 *
;*       ************                                                                                  *
;*        **********                                                                                   *
;*                                                                                                     *
;*******************************************************************************************************
;* This module provides time optimized CC2400 FIFO read and write functions.													 *
;* Function calls are made from main.c. The location and boundaries of rx and tx buffers are built		 *
;* directly in to the pointer operations.																															 *
;*******************************************************************************************************
;* Assembler: Keil A51                                                                                  *
;* Target platform:  8051F005                                                                          *
;*******************************************************************************************************
;* Revision history:   																					 																	     *
;* Initial release, HKI, 01.08.2004    			                                                      		 *
;******************************************************************************************************/

NAME FIF0

#include <ASMinclude.h>


?PR?readFIFO?FIFO  	SEGMENT CODE 
?PR?writeFIFO?FIFO  SEGMENT CODE 


PUBLIC readFIFO 
PUBLIC writeFIFO


;******************************************************************************************************
;* 																						Functions					   							                		  *
;******************************************************************************************************

; Read in from FIFO. Fixed at 16 bytes.
; Register Bank 2 holds the XDATA address bytes for write 
; operations to rxBuffer (first write to 0x00, decrementing to 0xFF).
; Note that setup instructions normally located at the start of a function
; are executed while data is shifted on SPI. Pointers are also prepared
; while waiting for the SPI, resulting in more messy, but more efficient code.

RSEG	?PR?readFIFO?FIFO
readFIFO:
		
		PUSH	PSW	

		CLR  	M_SPI_CS
		
		MOV  	SPI0DAT, #0xF0							; CC2400_FIFOREG (read strobe)

		MOV		PSW, #0x10									; Register Bank 2
		MOV		PAGEREG, rxBufferWritePage	; Restore upper byte of data pointer

		MOV		R7, A												; Note! MOV R7, A cannot precede a instruction that changes RS0/RS1 (p75, 8051 Data sheet)


		DEC		rxBufferWriteLowB						; Pre-decrement

		MOV		byteCount, #0x0F						; SPI_RX byte counter
																			
SPI_WAIT_1:														; Wait for read strobe to shift out
		JNB  	SPIF, SPI_WAIT_1
		CLR  	SPIF

		MOV  	SPI0DAT, A									; Set SPI0DAT to some value to start to shift in first byte

		NOP																; Using NOPs to get the exact number of cycles necessary
		NOP																; 10 cycles
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		NOP
		SJMP	START_SPI_RX							  ; The SPI_RX loop is time optimized. Need to jump to the SPI_WAIT
																			; as the first byte is already being shifted in.
SPI_RX:																; The RX loop takes a few more cycles than the SPI shift operation-
		MOVX	@rxBufferWriteLowB, A				; a separate header loop is required if more bytes must be processed at this stage.
		MOV		nextByte, A									; Write byte to temporary storage
		MOV		A, rxBufferWriteLowB				; If 0x00 -> seqNo
		JNZ   NOT_SEQNO

		MOV		A, seqNoPtr									; Check seqNo against previous
		XRL		A, nextByte
		JNZ		SEQNO_OK

		ORL		systemFlagsPtr, #0x01				; Set flag is this sequence number is the same as the last

SEQNO_OK:
		MOV		seqNoPtr, nextByte

		SJMP	END_HEADER_CHECK

NOT_SEQNO:		
		CPL		A														; If 0x00 (rxBufferWriteLowB == 0xFF) -> sysID
		JNZ		NOT_SYSID
		
		MOV		A, #SYS_ID									; Check sysID
		XRL		A, nextByte
		JZ		SYSID_OK

		ORL		systemFlagsPtr, #0x04	

SYSID_OK:
NOT_SYSID:
END_HEADER_CHECK:
		DEC		rxBufferWriteLowB

START_SPI_RX:	
		CLR  	SPIF

		XCH		A, SPI0DAT									; Shif-in complete - read byte and start next shift

		DJNZ	byteCount, SPI_RX	

		MOVX	@rxBufferWriteLowB, A				; Write byte to rxBuffer
		
		DEC		rxBufferWriteLowB

		CJNE 	rxBufferWriteLowB, #0x01, STILL_ON_RX_PAGE
		DEC		PAGEREG			
		ANL		PAGEREG, #0x03						  ; Make sure we stay within the 1024 byte buffer
		MOV		rxBufferWritePage, PAGEREG	; Save, ready for next call to readFIFO()
		INC		PAGEREG											; Must reset for last byte
		ANL		PAGEREG, #0x03

STILL_ON_RX_PAGE:
SPI_WAIT_2:													
		JNB  	SPIF, SPI_WAIT_2
		CLR  	SPIF
													
		MOV  	A, SPI0DAT									; Read last byte
		MOVX	@rxBufferWriteLowB, A	
				
		SETB	M_SPI_CS
		MOV		A, R7
		POP		PSW	

		RET

;*******************************************************************************************************

; Write out to FIFO. Fixed at 16 bytes.
; Register Bank 2 holds the XDATA address bytes for read 
; operations from txBuffer (first read from 0x00, decrementing to 0xFF).
; Note that setup instructions normally located at the start of a function
; are executed while data is shifted on SPI. Pointers are also prepared
; while waiting for the SPI, resulting in more messy, but more efficient code.

RSEG	?PR?writeFIFO?FIFO
writeFIFO:

		PUSH	PSW	

		CLR  	M_SPI_CS

		MOV		SPI0DAT, #0x70							; CC2400_FIFO (write strobe)

		MOV		PSW, #0x10									; Register Bank 2
		MOV		PAGEREG, txBufferReadPage		; Restore upper byte of data pointer
		MOV		R7, A
		
		MOV		byteCount, #0x0F						; SPI_TX byte counter

		DEC		txBufferReadLowB
		MOVX	A, @txBufferReadLowB

		SJMP  START_SPI_TX								
																			
SPI_TX:															
		DEC		txBufferReadLowB
		MOVX	A, @txBufferReadLowB

		NOP																; 8 cycles
		NOP
		NOP
		NOP
		NOP		
		NOP
		NOP
		NOP

START_SPI_TX:
		CLR		SPIF

		MOV		SPI0DAT, A									; Write out next byte

		DJNZ	byteCount, SPI_TX

		DEC		txBufferReadLowB
		MOVX	A, @txBufferReadLowB

		CJNE 	txBufferReadLowB, #0x01, STILL_ON_TX_PAGE
		DEC		PAGEREG
		ANL		PAGEREG, #0x03							; Make sure we stay within the 1024 byte buffer					
		MOV		txBufferReadPage, PAGEREG		; Save after change

STILL_ON_TX_PAGE:

SPI_WAIT_3:														
		JNB		SPIF, SPI_WAIT_3
		CLR		SPIF

		MOV		SPI0DAT, A									; Write last byte

		MOV		A, R7
		POP		PSW	

SPI_WAIT_4:
		JNB		SPIF, SPI_WAIT_4
		CLR		SPIF

		SETB	M_SPI_CS
		
		RET

;*******************************************************************************************************

END