boot.s

sl811hs 的驱动

 ;2003/4/11 
 ;today, I have finished boot from sdram, a notable progress. I am very excited.
 ;I name the version is V2.0
 ;the detail information refer to my notebook
 
   GET board.h   
   GET sreg.h  
    
 AREA boot,CODE,READONLY
     
    IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
    IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
    IMPORT |Image$$ZI$$Base| ; Base & limit of area
    IMPORT |Image$$ZI$$Limit| ; to zero initialise
    
    IMPORT |Image$$RO$$Base|      ;===============test
    IMPORT |Image$$RW$$Limit|
 
 ENTRY
 
 B Reset_Handler              ;address=0x0000
 B SystemUndefinedHandler     ;Undefined_Handler                  0x0004
 B SystemSwiHandler           ;SWI_Handler                        0x0008
 B SystemPrefetchHandler      ;Prefetch_Handler                   0x000C
 B SystemAbortHandler         ;Abort_Handler                      0x0010
 NOP                          ;        0x0014   reserved
 B SystemIrqHandler           ;IRQ_Handler                        0x0018
 B SystemFiqHandler           ;FIQ_Handler                        0x001C
 
Reset_Handler
 ;==============================================
 ;        SDRAM & FLASH CONFIGRATION
 ;==============================================

    LDR r0, =SYSCFG
    LDR r1, =dSYSCFG
    STR r1, [r0]
    
    LDR r0, =SystemInitData
    LDMIA r0, {r1-r12}
    LDR r0, =EXTDBWTH
    STMIA r0, {r1-r12}
    
 ;==============================================
 ;   transfer the codes from flash to sdram
 ;==============================================
 
     LDR r0, =|Image$$RO$$Base|
     LDR r1, =|Image$$RO$$Limit|
     LDR r2, =DRAM_BASE
     
     SUB r1, r1, r0
     ADD r1, r1, #4
     
CODE_LOOP
     LDR r3, [r0], #4
     STR r3, [r2], #4
     SUBS r1, r1, #4
     BNE  CODE_LOOP
     
 
 ;===============================================
 ;   change base address of rom and sdram
 ;===============================================
    
    LDR r0, =SystemInitData_S
    LDMIA r0, {r1-r12}
    LDR r0, =EXTDBWTH
    STMIA r0, {r1-r12}

 ;===========================================
 ;       initialize stack
 ;===========================================

 ;after reseted, 4510 has been in SVC mode.
    
INITIALIZE_STACK
    
    MRS r0, cpsr                       ;now, 4510 is in SVC mode
    BIC r0, r0, #LOCKOUT | MODE_MASK   ;LOCKOUT|MODE_MASK=1101,1111,~=0010,0000
    ORR r2, r0, #USR_MODE              ;save[31..8] & T bit. 
    
    ORR r1, r0, #LOCKOUT | FIQ_MODE    ;change mode & mask irq &frq
    MSR cpsr_cxsf, r1                       
    MSR spsr_cxsf, r2                       ;save user mode
    LDR sp, =FIQ_STACK
    
    ORR r1, r0, #LOCKOUT | IRQ_MODE
    MSR cpsr_cxsf, r1
    MSR spsr_cxsf, r2
    LDR sp, =IRQ_STACK
    
    ORR r1, r0, #LOCKOUT | ABT_MODE
    MSR cpsr_cxsf, r1
    MSR spsr_cxsf, r2
    LDR sp, =ABT_STACK
    
    ORR r1, r0, #LOCKOUT | UDF_MODE
    MSR cpsr_cxsf, r1
    MSR spsr_cxsf, r2
    LDR sp, =UDF_STACK
    
    ORR r1, r0, #LOCKOUT | SVC_MODE
    MSR cpsr_cxsf, r1
    MSR spsr_cxsf, r2
    LDR sp, =SVC_STACK                ; Change CPSR to SVC mode
    
    ;the stack for user is init in later.
    
;================================================
;    INITIALISE MEMORY REQUIRED BY C CODE
;================================================
    LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
    LDR r1, =|Image$$RW$$Base| ;  RAM copy
    LDR r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
    
    CMP r0, r1 ; Check that they are different
    BEQ %1
0   CMP r1, r3 ; Copy init data
    LDRCC r2, [r0], #4
    STRCC r2, [r1], #4
    BCC %0
1   LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    MOV r2, #0
2   CMP r3, r1 ; Zero init
    STRCC r2, [r3], #4          ;if r3<r1, so init these cells to be 0.
    BCC %2


;================================================
;  change to user mode & set up user mode stack
;================================================
    MRS r0, cpsr
    BIC r0, r0, #LOCKOUT | MODE_MASK
    ORR r1, r0, #USR_MODE
    MSR cpsr_cxsf, r1
    LDR sp, =USR_STACK
    
;================================================
;               enter c program
;================================================
   
    IMPORT C_entry
    BL C_entry
    
;note:
;interupt init is charge of user code.
;in user code, the first process is set interrupt(irq,fiq),
;clear pend bits,set priority, start apropriate interrupt. 


;=============================================
;    EXCEPTION_VENDOR_FUNCTION
;============================================= 
 
SystemUndefinedHandler
    
    IMPORT ISR_UndefHandler       ;ISR_UndefHandler is c code in isr.c
    STMFD sp!, {r0-r12}
    B ISR_UndefHandler
    LDMFD sp!, {r0-r12, pc}^

    
SystemSwiHandler
    STMFD sp!, {r0-r12,lr}
    LDR r0, [lr, #-4]
    BIC r0, r0, #0xff000000
    CMP r0, #0xff
    BEQ MakeSVC
    LDMFD sp!, {r0-r12, pc}^
MakeSVC
    MRS r1, spsr
    BIC r1, r1, #MODE_MASK
    ORR r2, r1, #SVC_MODE
    MSR spsr_cxsf, r2
    LDMFD sp!, {r0-r12, pc}^

    
SystemPrefetchHandler
    IMPORT ISR_PrefetchHandler      ;ISR_PrefetchHandler is c code in isr.c
    STMFD sp!, {r0-r12, lr}
    B ISR_PrefetchHandler
    LDMFD sp!, {r0-r12, lr}
    ;ADD sp, sp, #4
    SUBS pc, lr, #4

    
SystemAbortHandler
    IMPORT ISR_AbortHandler         ;ISR_AbortHandler is c code in isr.c
    STMFD sp!, {r0-r12, lr}
    B ISR_AbortHandler
    LDMFD sp!, {r0-r12, lr}
    ;ADD sp, sp, #4
    SUBS pc, lr, #8


SystemReserv
    SUBS pc, lr, #4

    
SystemIrqHandler
    IMPORT ISR_IrqHandler
    STMFD sp!, {r0-r12,lr}
    BL ISR_IrqHandler    
    LDMFD sp!, {r0-r12,lr}
    SUBS pc, lr, #4


SystemFiqHandler
    IMPORT ISR_FiqHandler   
    STMFD sp!, {r0-r7, lr}
    BL ISR_FiqHandler
    LDMFD sp!, {r0-r7, lr}
    SUBS pc, lr, #4
    
    
;**********************************************************************
 AREA ROMDATA,DATA,READONLY 
;******************SDARM SYSTEM INITIALIZE DATA************************
SystemInitData
    DCD  dEXTDBWTH
    DCD  dROMCON0
    DCD  dROMCON1
    DCD  dROMCON2
    DCD  dROMCON3
    DCD  dROMCON4
    DCD  dROMCON5
    DCD  dDRAMCON0
    DCD  dDRAMCON1
    DCD  dDRAMCON2
    DCD  dDRAMCON3
    DCD  dREFEXTCON

SystemInitData_S
    DCD  dEXTDBWTH
    DCD  dROMCON0_S
    DCD  dROMCON1_S
    DCD  dROMCON2_S
    DCD  dROMCON3_S
    DCD  dROMCON4_S
    DCD  dROMCON5_S
    DCD  dDRAMCON0_S
    DCD  dDRAMCON1_S
    DCD  dDRAMCON2_S
    DCD  dDRAMCON3_S
    DCD  dREFEXTCON

;**********************************************************************
; AREA RAMDATA, DATA, READWRITE
 
;*********************************************************************
 AREA SYS_STACK, DATA, NOINIT
 
 ;note:determine the stack address when linking
      
             %  USR_STACK_SIZE
USR_STACK
             %  UDF_STACK_SIZE
UDF_STACK
             %  ABT_STACK_SIZE
ABT_STACK
             %  IRQ_STACK_SIZE
IRQ_STACK
             %  FIQ_STACK_SIZE
FIQ_STACK
             %  SVC_STACK_SIZE
SVC_STACK

                     END