📄 board.h
字号:
;**********************board allocation************************
;**************************************************************
;********************** SREG DATA *****************************
;**************************************************************
;********SYSTEM CONFIGURATION********
;data structure
;[31] [30 26] [25....16] [15....6] [5 4] [3] [2] [1] [0]
;SDM PD_ID Sreg_Basep I_Sarm_Base CM 0 WE CE SE
SYS_SE EQU 0x0 ;must be set to 0
SYS_CE EQU 0x1<<1 ;1,enable cache
SYS_WE EQU 0x1<<2 ;1,enable write buffer
SYS_CM EQU 0x1<<4 ;00=4KB SRAM,4KB CACHE
;01=0KB SRAM,8KB CACHE
;10=8KB SRAM,0KB CACHE
SYS_SRAM_BP EQU 0x3FE<<6 ;Sram base address from 0x3fe0000
SYS_SREG_BP EQU 0x3FF<<16 ;Sreg base address from 0x3ff0000
SYS_SDM EQU 0x1<<31 ;use sdram
dSYSCFG EQU SYS_SDM+SYS_SREG_BP+SYS_SRAM_BP+SYS_CM+SYS_WE+SYS_CE+SYS_SE
;********CLK CONTROL REG*************
;data structure
;[31] [19 18] [17] [16] [15....0]
;Test ROM5_C ROM5_E ROM5_W CLK_DIV
CLK_DIV EQU 0x0
ROM5_W EQU 0x0<<16
ROM5_E EQU 0x0<<17
ROM5_C EQU 0x0<<18
TEST EQU 0x0<<31 ;equal to 1, test mode
dCLKCON EQU TEST+ROM5_C+ROM5_E+ROM5_W+CLK_DIV
;********FLASH/ROM/SRAM**************
;data structure
;[31 30] [29........20] [19........10] [9] [8] [7] [6..4] [3 2] [1 0]
; 0 0 Next_p Base_p 0 0 0 Tacc Tpa Pmc
;********BANK0--FLASH*********
ROMBASEP0 EQU 0x000<<10
ROMNEXTP0 EQU 0x008<<20 ;1M+1 FLASH0 address from 0x0 to 0x0080000(4M),include 0x0080000
ROMBASEP0_S EQU 0x080<<10
ROMNEXTP0_S EQU 0x088<<20
;__parameter defination
PMC0 EQU 0x0 ;00=Normal ROM, 01=4-word page, 10=8-word page, 11=16-word page
TPA0 EQU 0x0<<2 ;00=5cycles, 01=2cycles, 10=3cycles, 11=4cycles
TACC0 EQU 0x6<<4 ;000=Disable bank, 001=2cycles, 010=3cycles, 011=4cycles
;110=7cycles, 111=reserved
dROMCON0 EQU ROMNEXTP0+ROMBASEP0+TACC0+TPA0+PMC0
dROMCON0_S EQU ROMNEXTP0_S+ROMBASEP0_S+TACC0+TPA0+PMC0
;********BANK1--FLASH*********
ROMBASEP1 EQU 0x000<<10
ROMNEXTP1 EQU 0x000<<20
ROMBASEP1_S EQU 0x000<<10
ROMNEXTP1_S EQU 0x000<<20
;__parameter defination
PMC1 EQU 0x0
TPA1 EQU 0x0<<2
TACC1 EQU 0x6<<4
dROMCON1 EQU ROMNEXTP1+ROMBASEP1+TACC1+TPA1+PMC1
dROMCON1_S EQU ROMNEXTP1_S+ROMBASEP1_S+TACC1+TPA1+PMC1
;********BANK2--FLASH*********
ROMBASEP2 EQU 0x000<<10
ROMNEXTP2 EQU 0x000<<20
ROMBASEP2_S EQU 0x000<<10
ROMNEXTP2_S EQU 0x000<<20
;__parameter defination
PMC2 EQU 0x0
TPA2 EQU 0x0<<2
TACC2 EQU 0x6<<4
dROMCON2 EQU ROMNEXTP1+ROMBASEP1+TACC1+TPA1+PMC1
dROMCON2_S EQU ROMNEXTP1_S+ROMBASEP1_S+TACC1+TPA1+PMC1
;********BANK3--FLASH*********
ROMBASEP3 EQU 0x000<<10
ROMNEXTP3 EQU 0x000<<20
ROMBASEP3_S EQU 0x000<<10
ROMNEXTP3_S EQU 0x000<<20
;__parameter defination
PMC3 EQU 0x0
TPA3 EQU 0x0<<2
TACC3 EQU 0x6<<4
dROMCON3 EQU ROMNEXTP1+ROMBASEP1+TACC1+TPA1+PMC1
dROMCON3_S EQU ROMNEXTP1_S+ROMBASEP1_S+TACC1+TPA1+PMC1
;********BANK4--FLASH*********
ROMBASEP4 EQU 0x000<<10
ROMNEXTP4 EQU 0x000<<20
ROMBASEP4_S EQU 0x000<<10
ROMNEXTP4_S EQU 0x000<<20
;__parameter defination
PMC4 EQU 0x0
TPA4 EQU 0x0<<2
TACC4 EQU 0x6<<4
dROMCON4 EQU ROMNEXTP1+ROMBASEP1+TACC1+TPA1+PMC1
dROMCON4_S EQU ROMNEXTP1_S+ROMBASEP1_S+TACC1+TPA1+PMC1
;********BANK5--FLASH*********
ROMBASEP5 EQU 0x000<<10
ROMNEXTP5 EQU 0x000<<20
ROMBASEP5_S EQU 0x000<<10
ROMNEXTP5_S EQU 0x000<<20
;__parameter defination
PMC5 EQU 0x0
TPA5 EQU 0x0<<2
TACC5 EQU 0x6<<4
dROMCON5 EQU ROMNEXTP1+ROMBASEP1+TACC1+TPA1+PMC1
dROMCON5_S EQU ROMNEXTP1_S+ROMBASEP1_S+TACC1+TPA1+PMC1
;********DRAM/SDRAM******************
;data structure
;[31 31] [29.....20] [19......10] [9 8] [7] [6..4] [3] [2 1] [0]
; Can Next_p Base_p Trp Trc Res Tcp Tcs Edo
;********BANK0--SDRAM********
DRAMBASEP0 EQU 0x080<<10
DRAMNEXTP0 EQU 0x0C0<<20 ;4M SDRAM0 address from 0x0800000 to 0x0c00000
DRAMBASEP0_S EQU 0x000<<10
DRAMNEXTP0_S EQU 0x040<<20
;__parameter defination
CAN0 EQU 0x0<<31 ;column address bits
;00=8bits, 01=9bits, 10=10bits, 11=11bits
TRP0 EQU 0x3<<8 ;00=1cycle, 01=2cycles, 10=3cycles, 11=4cycles
TRC0 EQU 0x1<<7 ;0=1cycles, 1=2cycles
RES0 EQU 0x1<<4 ;value is 000, but we must set to 001(refer to datasheet)
TCP0 EQU 0x1<<3 ;0=1cycles, 1=2cycles
TCS0 EQU 0x0<<1 ;00=1 cycle, 01=2 cycles, 10=3cycles, 11=4cycles
EDO0 EQU 0x0 ;0=Normal DRAM, 1=EDO DRAM
dDRAMCON0 EQU CAN0+DRAMNEXTP0+DRAMBASEP0+TRP0+TRC0+RES0+TCP0+TCS0+EDO0
dDRAMCON0_S EQU CAN0+DRAMNEXTP0_S+DRAMBASEP0_S+TRP0+TRC0+RES0+TCP0+TCS0+EDO0
;********BANK1--DRAM*********
DRAMBASEP1 EQU 0x000<<10
DRAMNEXTP1 EQU 0x000<<20
DRAMBASEP1_S EQU 0x000<<10
DRAMNEXTP1_S EQU 0x000<<20
;__parameter defination
CAN1 EQU 0x0<<31
TRP1 EQU 0x3<<8
TRC1 EQU 0x1<<7
RES1 EQU 0x1<<4
TCP1 EQU 0x1<<3
TCS1 EQU 0x0<<1
EDO1 EQU 0x0
dDRAMCON1 EQU CAN1+DRAMNEXTP1+DRAMBASEP1+TRP1+TRC1+RES1+TCP1+TCS1+EDO1
dDRAMCON1_S EQU CAN1+DRAMNEXTP1_S+DRAMBASEP1_S+TRP1+TRC1+RES1+TCP1+TCS1+EDO1
;********BANK2--DRAM*********
DRAMBASEP2 EQU 0x000<<10
DRAMNEXTP2 EQU 0x000<<20
DRAMBASEP2_S EQU 0x000<<10
DRAMNEXTP2_S EQU 0x000<<20
;__parameter defination
CAN2 EQU 0x0<<31
TRP2 EQU 0x3<<8
TRC2 EQU 0x1<<7
RES2 EQU 0x1<<4
TCP2 EQU 0x1<<3
TCS2 EQU 0x0<<1
EDO2 EQU 0x0
dDRAMCON2 EQU CAN2+DRAMNEXTP2+DRAMBASEP2+TRP2+TRC2+RES2+TCP2+TCS2+EDO2
dDRAMCON2_S EQU CAN2+DRAMNEXTP2_S+DRAMBASEP2_S+TRP2+TRC2+RES2+TCP2+TCS2+EDO2
;********BANK3--DRAM*********
DRAMBASEP3 EQU 0x000<<10
DRAMNEXTP3 EQU 0x000<<20
DRAMBASEP3_S EQU 0x000<<10
DRAMNEXTP3_S EQU 0x000<<20
;__parameter defination
CAN3 EQU 0x0<<31
TRP3 EQU 0x3<<8
TRC3 EQU 0x1<<7
RES3 EQU 0x1<<4
TCP3 EQU 0x1<<3
TCS3 EQU 0x0<<1
EDO3 EQU 0x0
dDRAMCON3 EQU CAN3+DRAMNEXTP3+DRAMBASEP3+TRP3+TRC3+RES3+TCP3+TCS3+EDO3
dDRAMCON3_S EQU CAN3+DRAMNEXTP3_S+DRAMBASEP3_S+TRP3+TRC3+RES3+TCP3+TCS3+EDO3
;********DATA BUS WIDTH**************
;data structure
;[..][27 26][25 24][23 21][21 20][19 18][17 16][15 14][13 12][11 10][9 8][7 6][5 4][3 2][1 0]
;0000 DSX3 DSX2 DSX1 DSX0 DSD3 DSD2 DSD1 DSD0 DSR5 DSR4 DSR3 DSR2 DSR1 DSR0
;00=disable, 01=8bits, 10=16bits, 11=32bits
DSR0 EQU 0x2 ;FLASH0--16bits
DSR1 EQU 0x0<<2
DSR2 EQU 0x0<<4
DSR3 EQU 0x0<<6
DSR4 EQU 0x0<<8
DSR5 EQU 0x0<<10
DSD0 EQU 0x2<<12 ;SDRAM0--16bits
DSD1 EQU 0x0<<14
DSD2 EQU 0x0<<16
DSD3 EQU 0x0<<18
DSX0 EQU 0x3<<20 ;EXT_BANK0--32bits edit by chendong 04-05-28 10:44
DSX1 EQU 0x3<<22 ;EXT_BANK1--32bits edit by chendong 04-03-05 11:50
DSX2 EQU 0x1<<24 ;EXT_BANK2--8bits edit by chendong 04-03-31 10:31
DSX3 EQU 0x0<<26
dEXTDBWTH EQU DSX3+DSX2+DSX1+DSX0+DSD3+DSD2+DSD1+DSD0+DSR5+DSR4+DSR3+DSR2+DSR1+DSR0
;********REFRESH CONTROL*************
;data structure
;[31...21] [20] [19 17] [16] [15] [14..10] [9....0]
;Ref_Value Tcsr Trc Ren Vsf 00000 Ext_Basep
EXT_BASEP EQU 0x3FC ;ext address from 0x3fc0000
VSF EQU 0x1<<15 ;0=NOT accessible to mem bank, 1=accessible to mem bank
REN EQU 0x1<<16 ;1=enable refresh, 0=disable refresh
TRC EQU 0x0<<17 ;000=1cycle 101=6cycles(sdram) 110 111 unused
TCSR EQU 0x0<<20 ;cas setup time 0=1cycle 1=2cycles
REF_VALUE EQU 0x4E1<<21 ;once refresh, 800 clocks
dREFEXTCON EQU REF_VALUE+TCSR+TRC+REN+VSF+EXT_BASEP
;********EXTCON CONFIG**************
;**********EXTACON0***************** ;edit by chendong 04-03-04 15:44
;data structure
;[31..28] [27..25] [24..22] [21..19] [18..16] [15..12] [11..9] [8..6] [5..3] [2..0]
; 0000 tACC1 tCOH1 tACS1 tCOS1 0000 tACC0 tCOH0 tACS0 tCOS0
;000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycles 010 = 2 cycles 110 = 6 cycles 011 = 3 cycles 111 = 7 cycles
tACC1 EQU 0x7<<25 ;set EXTACON0 mode--tACS1=0cycle tACC1=7cycle tCOS1=1cycle tCOH1=1cycle
tCOH1 EQU 0x1<<22
tACS1 EQU 0x0<<19
tCOS1 EQU 0x1<<16
tACC0 EQU 0x0<<9
tCOH0 EQU 0x0<<6
tACS0 EQU 0x0<<3
tCOS0 EQU 0x0<<0
dEXTACON0 EQU tACC1+tCOH1+tACS1+tCOS1+tACC0+tCOH0+tACS0+tCOS0
;**********EXTACON1***************** ;edit by chendong 04-05-07 11:11
;data structure
;[31..28] [27..25] [24..22] [21..19] [18..16] [15..12] [11..9] [8..6] [5..3] [2..0]
; 0000 tACC3 tCOH3 tACS3 tCOS3 0000 tACC2 tCOH2 tACS2 tCOS2
;000 = 0 cycle 100 = 4 cycles 001 = 1 cycle 101 = 5 cycles 010 = 2 cycles 110 = 6 cycles 011 = 3 cycles 111 = 7 cycles
tACC3 EQU 0x0<<25
tCOH3 EQU 0x0<<22
tACS3 EQU 0x0<<19
tCOS3 EQU 0x0<<16
tACC2 EQU 0x1<<9
tCOH2 EQU 0x1<<6
tACS2 EQU 0x0<<3
tCOS2 EQU 0x1<<0
dEXTACON1 EQU tACC3+tCOH3+tACS3+tCOS3+tACC2+tCOH2+tACS2+tCOS2
;*******************************************************************
;******************* memory allocation *****************************
;*******************************************************************
;***********************SYS_STACK***********************************
;define stack size of every mode
;STACK_BASE EQU DRAMBASEP0+0x1370000 ;0x1370000 ---- C$$ZIDATA$$LIMIT
USR_STACK_SIZE EQU 1024 ;user mode
UDF_STACK_SIZE EQU 512 ;undefined mode
ABT_STACK_SIZE EQU 512 ;abort mode
IRQ_STACK_SIZE EQU 2048 ;irq mode
FIQ_STACK_SIZE EQU 2048 ;fiq mode
SVC_STACK_SIZE EQU 2048 ;supervisor
SYS_STACK_SIZE EQU 1024*8 ;define 8k system stack
;**************** exception handler vector table *******************
DRAM_BASE EQU (DRAMBASEP0>>10)<<16
DRAM_LIMIT EQU (DRAMNEXTP0>>20)<<16
EXCEPTION_SIZE EQU 0x50
EXCEPTION_TABLE EQU DRAM_BASE+EXCEPTION_SIZE
;defination in boot.s
;*******************************************************************
;*********************** mode defination ***************************
;*******************************************************************
;mode defination
USR_MODE EQU 0x10
FIQ_MODE EQU 0x11
IRQ_MODE EQU 0x12
SVC_MODE EQU 0x13
ABT_MODE EQU 0x17
UDF_MODE EQU 0x1B
MODE_MASK EQU 0x1F
LOCKOUT EQU 0xC0 ;mask(1) irq, fiq, & use arm instructor
;********************************************************************
END⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -