📄 fat32.lst
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161 =1 // SPI control 0
162 =1 #define SPI_LSB 0x1
163 =1 #define SPI_CPOL 0x2
164 =1 #define SPI_CPHA 0x4
165 =1 #define SPI_MST 0x8
166 =1 #define SPI_TIE 0x10
167 =1 #define SPI_RIE 0x20
168 =1 #define SPI_EN 0x40
169 =1 #define SPI_SSOEN 0x80
170 =1 // SPI control 1
171 =1 #define SPI_3M 0x0
172 =1 #define SPI_1P5M 0x1
173 =1 #define SPI_750K 0x2
174 =1 #define SPI_375K 0x3
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175 =1 #define SPI_188K 0x4
176 =1 #define SPI_94K 0x5
177 =1 #define SPI_47K 0x6
178 =1 #define SPI_23K 0x7
179 =1 // SPI status
180 =1 #define SPI_SPTEF 0x1
181 =1 #define SPI_RRDY 0x2
182 =1 #define SPI_WERR 0x4
183 =1 #define SPI_RERR 0x8
184 =1 // SD control
185 =1 #define SD_64B 0x0
186 =1 #define SD_128B 0x1
187 =1 #define SD_256B 0x2
188 =1 #define SD_512B 0x3
189 =1 #define SD_WR 0x40
190 =1 #define SD_EN 0x80
191 =1 // SD status 0
192 =1
193 =1 // SD status 1
194 =1 #define SD_SDERR 0x1
195 =1 #define SD_SDINT 0x2
196 =1 #define SD_CMDEND 0x4
197 =1
198 =1 #define SD_DETECT 0x4
199 =1
200 =1 // Buffer Control
201 =1 #ifdef OLD_CHIP
202 =1 #define MCU2MP3 0x03
203 =1 #define USB2MP3 0x13
204 =1 #else
=1 #define MCU2MP3 0x02
=1 #define USB2MP3 0x12
=1 #endif
208 =1 #define USB2MCU 0x10
209 =1 #define MCU2USB 0x01
210 =1 #define USBFLSH 0x14
211 =1
212 =1 // function prototypes
213 =1 unsigned short WordSwap(unsigned short input);
214 =1 void DelayMs(unsigned int nFactor);
215 =1 void DelayUs(unsigned char nFactor);
216 =1 unsigned long SwapINT32(unsigned long dData);
217 =1 unsigned char SendUart(unsigned char *pUsrBuf, unsigned int num);
218 =1
219 =1
220 =1
3 #include "Fat.h"
1 =1 unsigned long FirstSectorofCluster(unsigned int n);
2 =1 unsigned int ThisFatEntOffset(unsigned int clusterNum);
3 =1 unsigned int GetNextClusterNum(unsigned int clusterNum);
4 =1 unsigned int ThisFatSecNum(unsigned int clusterNum);
4 #include "Fat32.h"
1 =1 //////////////////////////////////////////////////////////////////////
2 =1 unsigned long FirstSectorofCluster32(unsigned long clusterNum);
3 =1 unsigned long ThisFatSecNum32(unsigned long clusterNum);
4 =1 unsigned long ThisFatEntOffset32(unsigned long clusterNum);
5 =1 unsigned long GetNextClusterNum32(unsigned long clusterNum );
6 =1 unsigned char GoToPointer32(unsigned long pointer);
7 =1 unsigned char DeleteClusterLink32(unsigned long clusterNum);
8 =1 unsigned long GetFreeCusterNum32(void);
9 =1 unsigned long CreateClusterLink32(unsigned long currentCluster);
5 #include "SL811.H"
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1 =1 #define BYTE unsigned char
2 =1 #define WORD unsigned short
3 =1 #define ISO_BIT 0x10
4 =1 #define MAX_EP 0x05 // maximum number of endpoints (Ep0 + max of 4 data endpoints)
5 =1
6 =1 //*****************************************************************************************
7 =1 // Constant Defines
8 =1 //*****************************************************************************************
9 =1
10 =1 #define TIMEOUT_RETRY 0x06 // Maximum no. of timeout retry during USB xfer
11 =1
12 =1 typedef struct
13 =1 {
14 =1 WORD wVID, wPID; // Vendor ID and Product ID
15 =1 BYTE bClass; //
16 =1 BYTE bNumOfEPs; // actual number endpoint from slave
17 =1 BYTE iMfg; // Manufacturer ID
18 =1 BYTE iPdt; // Product ID
19 =1 BYTE bId1;
20 =1 BYTE bId2;
21 =1 BYTE bEPAddr[MAX_EP]; // bit 7 = 1 = use PID_IN,
22 =1 BYTE bAttr[MAX_EP]; // ISO | Bulk | Interrupt | Control
23 =1 WORD wPayLoad[MAX_EP]; // ISO range: 1-1023, Bulk: 1-64, etc
24 =1 WORD bInterval[MAX_EP]; // polling interval (for LS)
25 =1 BYTE bData1[MAX_EP]; // DataToggle value
26 =1 } pUSBDEV;
27 =1
28 =1 typedef struct
29 =1 {
30 =1 BYTE bmRequest;
31 =1 BYTE bRequest;
32 =1 WORD wValue;
33 =1 WORD wIndex;
34 =1 WORD wLength;
35 =1 } SetupPKG;
36 =1
37 =1 typedef struct
38 =1 {
39 =1 unsigned char usbaddr;
40 =1 unsigned char endpoint;
41 =1 unsigned char pid;
42 =1 unsigned char wPayload;
43 =1 unsigned int wLen;
44 =1 unsigned char *buffer;
45 =1 SetupPKG setup;
46 =1 unsigned char epbulkin;
47 =1 unsigned char epbulkout;
48 =1
49 =1 } PKG;
50 =1
51 =1 //------------------------------------------------------------------------
52 =1 // EP0 use for configuration and Vendor Specific command interface
53 =1 //------------------------------------------------------------------------
54 =1 #define EP0_Buf 0x10 // define start of EP0 64-byte buffer
55 =1 #define EP1_Buf 0x40 // define start of EP1 64-byte buffer
56 =1
57 =1 /*-------------------------------------------------------------------------
58 =1 * SL811H Register Control memory map
59 =1 * --Note:
60 =1 * --SL11H only has one control register set from 0x00-0x04
61 =1 * --SL811H has two control register set from 0x00-0x04 and 0x08-0x0c
62 =1 *------------------------------------------------------------------------*/
C51 COMPILER V8.02 FAT32 09/19/2006 15:01:23 PAGE 8
63 =1
64 =1 #define EP0Control 0x00
65 =1 #define EP0Address 0x01
66 =1 #define EP0XferLen 0x02
67 =1 #define EP0Status 0x03
68 =1 #define EP0Counter 0x04
69 =1
70 =1 #define EP1Control 0x08
71 =1 #define EP1Address 0x09
72 =1 #define EP1XferLen 0x0a
73 =1 #define EP1Status 0x0b
74 =1 #define EP1Counter 0x0c
75 =1
76 =1 #define CtrlReg 0x05
77 =1 #define IntEna 0x06
78 =1 // 0x07 is reserved
79 =1 #define IntStatus 0x0d
80 =1 #define cDATASet 0x0e
81 =1 #define cSOFcnt 0x0f // Master=1 Slave=0, D+/D-Pol Swap=1 0=not [0-5] SOF Count
82 =1 // 0xAE = 1100 1110
83 =1 // 0xEE = 1110 1110
84 =1
85 =1 #define IntMask 0x57 /* Reset|DMA|EP0|EP2|EP1 for IntEna */
86 =1 #define HostMask 0x47 /* Host request command for IntStatus */
87 =1 #define ReadMask 0xd7 /* Read mask interrupt for IntStatus */
88 =1
89 =1 //Interrupt Status Mask
90 =1 #define USB_A_DONE 0x01
91 =1 #define USB_B_DONE 0x02
92 =1 #define BABBLE_DETECT 0x04
93 =1 #define INT_RESERVE 0x08
94 =1 #define SOF_TIMER 0x10
95 =1 #define INSERT_REMOVE 0x20
96 =1 #define USB_RESET 0x40
97 =1 #define USB_DPLUS 0x80
98 =1 #define INT_CLEAR 0xFF
99 =1
100 =1 //EP0 Status Mask
101 =1 #define EP0_ACK 0x01 // EPxStatus bits mask during a read
102 =1 #define EP0_ERROR 0x02
103 =1 #define EP0_TIMEOUT 0x04
104 =1 #define EP0_SEQUENCE 0x08
105 =1 #define EP0_SETUP 0x10
106 =1 #define EP0_OVERFLOW 0x20
107 =1 #define EP0_NAK 0x40
108 =1 #define EP0_STALL 0x80
109 =1
110 =1 /*-------------------------------------------------------------------------
111 =1 * Standard Chapter 9 definition
112 =1 *-------------------------------------------------------------------------
113 =1 */
114 =1 #define GET_STATUS 0x00
115 =1 #define CLEAR_FEATURE 0x01
116 =1 #define SET_FEATURE 0x03
117 =1 #define SET_ADDRESS 0x05
118 =1 #define GET_DESCRIPTOR 0x06
119 =1 #define SET_DESCRIPTOR 0x07
120 =1 #define GET_CONFIG 0x08
121 =1 #define SET_CONFIG 0x09
122 =1 #define GET_INTERFACE 0x0a
123 =1 #define SET_INTERFACE 0x0b
124 =1 #define SYNCH_FRAME 0x0c
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125 =1
126 =1
127 =1 #define DEVICE 0x01
128 =1 #define CONFIGURATION 0x02
129 =1 #define STRING 0x03
130 =1 #define INTERFACE 0x04
131 =1 #define ENDPOINT 0x05
132 =1
133 =1 #define STDCLASS 0x00
134 =1
135 =1 /*-------------------------------------------------------------------------
136 =1 * SL11H/SL811H definition
137 =1 *-------------------------------------------------------------------------
138 =1 */
139 =1
140 =1 // USB-A, USB-B Host Control Register [00H, 08H]
141 =1 // Pre Reserved
142 =1 // DatT Dir [1=Trans, 0=Recv]
143 =1 // SOF Enable
144 =1 // ISO Arm
145 =1 #define DATA0_WR 0x07 // 0000 0111 ( Data0 + OUT + Enable + Arm)
146 =1 #define sDATA0_WR 0x27 // 0010 0111 ( Data0 + SOF + OUT + Enable + Arm)
147 =1
148 =1 #define DATA0_RD 0x03 // 0000 0011 ( Data0 + IN + Enable + Arm)
149 =1 #define sDATA0_RD 0x23 // 0010 0011 ( Data0 + SOF + IN + Enable + Arm)
150 =1
151 =1 #define PID_SETUP 0xD0
152 =1 #define PID_IN 0x90
153 =1 #define PID_OUT 0x10
154 =1
155 =1
156 =1 unsigned char SL811_GetRev(void);
157 =1 void USBReset(void);
158 =1 unsigned char usbXfer(void);
159 =1 unsigned char ep0Xfer(void);
160 =1 unsigned char epBulkSend(unsigned char *pBuffer,unsigned int len);
161 =1 unsigned char epBulkRcv(unsigned char *pBuffer,unsigned int len);
162 =1 unsigned char SetAddress(unsigned char addr);
163 =1 unsigned char Set_Configuration(void);
164 =1
165 =1 unsigned char EnumUsbDev(BYTE usbaddr);
166 =1 void SL811_Init(void);
167 =1
168 =1 void check_key_LED(void);
169 =1
6 #include "TPBULK.H"
1 =1 #include "rbccmd.h"
1 =2 /*
2 =2 // RBC commands
3 =2 */
4 =2 #define RBC_CMD_FORMAT 0x04
5 =2 #define RBC_CMD_READ10 0x28
6 =2 #define RBC_CMD_READCAPACITY 0x25
7 =2 #define RBC_CMD_STARTSTOPUNIT 0x1B
8 =2 #define RBC_CMD_SYNCCACHE 0x35
9 =2 #define RBC_CMD_VERIFY10 0x2F
10 =2 #define RBC_CMD_WRITE10 0x2A
11 =2
12 =2 /*
13 =2 // SPC-2 commands
14 =2 */
15 =2 #define SPC_CMD_INQUIRY 0x12
C51 COMPILER V8.02 FAT32 09/19/2006 15:01:23 PAGE 10
16 =2 #define SPC_CMD_MODESELECT6 0x15
17 =2 #define SPC_CMD_MODESENSE6 0x1A
18 =2 #define SPC_CMD_PERSISTANTRESERVIN 0x5E
19 =2 #define SPC_CMD_PERSISTANTRESERVOUT 0x5F
20 =2 #define SPC_CMD_PRVENTALLOWMEDIUMREMOVAL 0x1E
21 =2 #define SPC_CMD_RELEASE6 0x17
22 =2 #define SPC_CMD_REQUESTSENSE 0x03
23 =2 #define SPC_CMD_RESERVE6 0x16
24 =2 #define SPC_CMD_TESTUNITREADY 0x00
25 =2 #define SPC_CMD_WRITEBUFFER 0x3B
26 =2 #define SPC_CMD_READLONG 0x23
27 =2
28 =2
29 =2 /*
30 =2 // ATAPI Command Descriptor Block - 13 Bytes
31 =2 */
32 =2
33 =2 typedef struct _READ_10 {
34 =2 UINT8 OperationCode;
35 =2 UINT8 Reserved1;
36 =2 UINT8 LBA_3;
37 =2 UINT8 LBA_2;
38 =2 UINT8 LBA_1;
39 =2 UINT8 LBA_0;
40 =2 UINT8 Reserved2;
41 =2 UINT8 XferLen_1;
42 =2 UINT8 XferLen_0;
43 =2 UINT8 Reserved3[3];
44 =2 } READ_10, *pREAD_10;
45 =2
46 =2 typedef struct _WRITE_10 {
47 =2 UINT8 OperationCode;
48 =2 UINT8 Reserved1;
49 =2 UINT8 LBA_3;
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