📄 08092.src
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; .\08092.SRC generated from: 08092.c
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE 08092.c BROWSE DEBUG OBJECTEXTEND SRC(.\08092.SRC)
$NOMOD51
NAME _08092
P0 DATA 080H
P1 DATA 090H
P2 DATA 0A0H
P3 DATA 0B0H
T0 BIT 0B0H.4
AC BIT 0D0H.6
T1 BIT 0B0H.5
T2 BIT 090H.0
EA BIT 0A8H.7
IE DATA 0A8H
OE BIT 0B0H.1
EXF2 BIT 0C8H.6
RD BIT 0B0H.7
ES BIT 0A8H.4
IP DATA 0B8H
RI BIT 098H.0
INT0 BIT 0B0H.2
CY BIT 0D0H.7
TI BIT 098H.1
INT1 BIT 0B0H.3
RCAP2H DATA 0CBH
PS BIT 0B8H.4
SP DATA 081H
T2EX BIT 090H.1
OV BIT 0D0H.2
RCAP2L DATA 0CAH
ST BIT 0B0H.0
C_T2 BIT 0C8H.1
WR BIT 0B0H.6
RCLK BIT 0C8H.5
TCLK BIT 0C8H.4
SBUF DATA 099H
PCON DATA 087H
SCON DATA 098H
TMOD DATA 089H
TCON DATA 088H
IE0 BIT 088H.1
IE1 BIT 088H.3
B DATA 0F0H
CP_RL2 BIT 0C8H.0
ACC DATA 0E0H
ET0 BIT 0A8H.1
ET1 BIT 0A8H.3
TF0 BIT 088H.5
ET2 BIT 0A8H.5
TF1 BIT 088H.7
TF2 BIT 0C8H.7
RB8 BIT 098H.2
TH0 DATA 08CH
EX0 BIT 0A8H.0
IT0 BIT 088H.0
TH1 DATA 08DH
TB8 BIT 098H.3
EX1 BIT 0A8H.2
IT1 BIT 088H.2
TH2 DATA 0CDH
P BIT 0D0H.0
SM0 BIT 098H.7
TL0 DATA 08AH
SM1 BIT 098H.6
TL1 DATA 08BH
SM2 BIT 098H.5
TL2 DATA 0CCH
PT0 BIT 0B8H.1
PT1 BIT 0B8H.3
RS0 BIT 0D0H.3
PT2 BIT 0B8H.5
TR0 BIT 088H.4
RS1 BIT 0D0H.4
EOC BIT 0B0H.2
TR1 BIT 088H.6
TR2 BIT 0C8H.2
PX0 BIT 0B8H.0
PX1 BIT 0B8H.2
CLK BIT 0B0H.3
DPH DATA 083H
DPL DATA 082H
EXEN2 BIT 0C8H.3
REN BIT 098H.4
T2CON DATA 0C8H
RXD BIT 0B0H.0
TXD BIT 0B0H.1
F0 BIT 0D0H.5
PSW DATA 0D0H
?PR?display?08092 SEGMENT CODE
?PR?main?08092 SEGMENT CODE
?PR?t0?08092 SEGMENT CODE
?PR?t1?08092 SEGMENT CODE
?C_INITSEG SEGMENT CODE
?CO?08092 SEGMENT CODE
?DT?08092 SEGMENT DATA
EXTRN CODE (?C?UIDIV)
EXTRN CODE (?C?IMUL)
EXTRN CODE (?C_STARTUP)
PUBLIC getdata
PUBLIC dispbit_select
PUBLIC dis
PUBLIC led_dispcode
PUBLIC t1
PUBLIC t0
PUBLIC main
PUBLIC display
RSEG ?DT?08092
dis: DS 10
dispbit_select: DS 8
getdata: DS 1
RSEG ?CO?08092
led_dispcode:
DB 03FH
DB 006H
DB 05BH
DB 04FH
DB 066H
DB 06DH
DB 07DH
DB 007H
DB 07FH
DB 06FH
RSEG ?C_INITSEG
DB 008H
DB dispbit_select
DW 000FEH
DW 000FDH
DW 000FBH
DW 000F7H
DB 00AH
DB dis
DW 00000H
DW 00000H
DW 00000H
DW 00000H
DW 00000H
; #include <reg52.H>
; #include <intrins.h>
; //#include <wait.h>
;
; unsigned char code led_dispcode[]={ 0x3f,0x06,0x5b,0x4f,0x66,
; 0x6d,0x7d,0x07,0x7f,0x6f};
; unsigned dispbit_select[4]={0xfe,0xfd,0xfb,0xf7};
; unsigned data dis[5]={0x00,0x00,0x00,0x00,0x00};
; unsigned char getdata;
;
; sbit ST=P3^0;
; sbit OE=P3^1;
; sbit EOC=P3^2;
; sbit CLK=P3^3;
;
; void display(void)
RSEG ?PR?display?08092
display:
USING 0
; SOURCE LINE # 16
; {
; SOURCE LINE # 17
; unsigned char k;
;
; dis[4]=getdata;
; SOURCE LINE # 20
MOV dis+08H,#00H
MOV dis+09H,getdata
; dis[3]=dis[4]/51;
; SOURCE LINE # 21
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+06H,R6
MOV dis+07H,R7
; dis[4]=dis[4]%51;
; SOURCE LINE # 22
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+08H,R4
MOV dis+09H,R5
; dis[4]=dis[4]*10;
; SOURCE LINE # 23
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#0AH
LCALL ?C?IMUL
MOV dis+08H,R6
MOV dis+09H,R7
; dis[2]=dis[4]/51;
; SOURCE LINE # 24
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+04H,R6
MOV dis+05H,R7
; dis[4]=dis[4]%51;
; SOURCE LINE # 25
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+08H,R4
MOV dis+09H,R5
; dis[4]=dis[4]*10;
; SOURCE LINE # 26
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#0AH
LCALL ?C?IMUL
MOV dis+08H,R6
MOV dis+09H,R7
; dis[1]=dis[4]/51;
; SOURCE LINE # 27
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+02H,R6
MOV dis+03H,R7
; dis[4]=dis[4]%51;
; SOURCE LINE # 28
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis+08H,R4
MOV dis+09H,R5
; dis[4]=dis[4]*10;
; SOURCE LINE # 29
MOV R6,dis+08H
MOV R7,dis+09H
MOV R4,#00H
MOV R5,#0AH
LCALL ?C?IMUL
MOV dis+08H,R6
MOV dis+09H,R7
; dis[0]=dis[4]/51;
; SOURCE LINE # 30
MOV R5,#033H
LCALL ?C?UIDIV
MOV dis,R6
MOV dis+01H,R7
;
; for(k = 0;k < 4;k++)
; SOURCE LINE # 32
;---- Variable 'k?040' assigned to Register 'R7' ----
CLR A
MOV R7,A
?C0001:
; {
; SOURCE LINE # 33
; P1=led_dispcode[dis[k]];
; SOURCE LINE # 34
MOV A,R7
ADD A,ACC
ADD A,#LOW (dis)
MOV R0,A
INC R0
MOV A,@R0
MOV DPTR,#led_dispcode
MOVC A,@A+DPTR
MOV P1,A
; if(k == 3){P1 = P1|0x80;}
; SOURCE LINE # 35
CJNE R7,#03H,?C0004
ORL P1,#080H
?C0004:
; P2 = dispbit_select[k];
; SOURCE LINE # 36
MOV A,R7
ADD A,ACC
ADD A,#LOW (dispbit_select)
MOV R0,A
INC R0
MOV A,@R0
MOV P2,A
; //Delay8us();
; P2 = 0xff;
; SOURCE LINE # 38
MOV P2,#0FFH
; }
; SOURCE LINE # 39
INC R7
CJNE R7,#04H,?C0001
; }
; SOURCE LINE # 40
?C0005:
RET
; END OF display
;
; void main(void)
RSEG ?PR?main?08092
main:
USING 0
; SOURCE LINE # 42
; {
; SOURCE LINE # 43
; TMOD = 0x02;
; SOURCE LINE # 44
MOV TMOD,#02H
; TH0 = 246;
; SOURCE LINE # 45
MOV TH0,#0F6H
; TL0 = 246;
; SOURCE LINE # 46
MOV TL0,#0F6H
; TH1=(65536-4000)/256;
; SOURCE LINE # 47
MOV TH1,#0F0H
; TL1=(65536-4000)%256;
; SOURCE LINE # 48
MOV TL1,#060H
; ET0 = 1;
; SOURCE LINE # 49
SETB ET0
; TR0 = 1;
; SOURCE LINE # 50
SETB TR0
; ET1 = 1;
; SOURCE LINE # 51
SETB ET1
; TR1 = 1;
; SOURCE LINE # 52
SETB TR1
; EA = 1;
; SOURCE LINE # 53
SETB EA
;
; ST = 0;
; SOURCE LINE # 55
CLR ST
; OE = 0;
; SOURCE LINE # 56
CLR OE
?C0006:
;
; while(1)
; SOURCE LINE # 58
; {
; SOURCE LINE # 59
; display();
; SOURCE LINE # 60
LCALL display
; }
; SOURCE LINE # 61
SJMP ?C0006
; END OF main
CSEG AT 0000BH
LJMP t0
; }
; void t0(void) interrupt 1 //using 0
RSEG ?PR?t0?08092
USING 0
t0:
PUSH PSW
; SOURCE LINE # 63
; {
; CLK = CLK^0x01;
; SOURCE LINE # 65
MOV C,CLK
CPL C
MOV CLK,C
; }
; SOURCE LINE # 66
POP PSW
RETI
; END OF t0
CSEG AT 0000BH
LJMP t1
; void t1(void) interrupt 1 using 0
RSEG ?PR?t1?08092
USING 0
t1:
; SOURCE LINE # 67
; {
; TH1=(65536-4000)/256;
; SOURCE LINE # 69
MOV TH1,#0F0H
; TL1=(65536-4000)%256;
; SOURCE LINE # 70
MOV TL1,#060H
; P0 = 0XFF;
; SOURCE LINE # 71
MOV P0,#0FFH
; ST = 1;
; SOURCE LINE # 72
SETB ST
; ST = 0;
; SOURCE LINE # 73
CLR ST
; _nop_();
; SOURCE LINE # 74
NOP
?C0010:
; while(EOC == 0);
; SOURCE LINE # 75
JNB EOC,?C0010
?C0011:
; OE = 1;
; SOURCE LINE # 76
SETB OE
; getdata = P0;
; SOURCE LINE # 77
MOV getdata,P0
; OE = 0;
; SOURCE LINE # 78
CLR OE
; } ; SOURCE LINE # 79
RETI
; END OF t1
END
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