verilog数字钟.txt

数字钟编译通过...大家下去直接用.支持程序员联合开发网

module clock(CLK,CLK_1K,MODE,CHANGE,TURN,ALERT,HOU,MIN,SEC,LD_AL,LD_H,LD_M);

input CLK,CLK_1K,MODE,CHANGE,TURN;

output [7:0] HOU,MIN,SEC;

output ALERT,LD_AL,LD_H,LD_M;

reg [7:0] HOU,MIN,SEC,THOU,TMIN,TSEC,AHOU,AMIN;

reg [1:0] m,fm,sound;

reg LD_H,LD_M;

reg CLK_1Hz,CLK_2Hz,mclk,hclk;

reg alert1,alert2,ear;

reg count1,count2,lcount1,lcount2;

wire ct1,ct2,lct1,lct2,m_clk,h_clk;

 

always @(posedge CLK)

begin

   CLK_2Hz<=~CLK_2Hz;

   if(sound==3)

      begin sound<=0;ear<=1;end

            //ear信号用于产生或屏蔽声音

   else 

      begin sound<=sound+1;ear<=0;end

end

 

always @(posedge CLK_2Hz)

   CLK_1Hz<=~CLK_1Hz; //产生1Hz的时基信号

 

always @(posedge MODE)   //MODE信号控制3钟功能的转换

   begin if(m==2) m<=0;  //m=0：计时功能

         else m<=m+1;    //m=1：闹钟功能

   end                   //m=2：手动校时

 

always @(TURN)

   fm<=~fm;     //校时时选择调整分钟还是小时

 

always

begin case(m)

      2:begin if(fm)

                 begin

                   count1<=CHANGE;

                   {LD_H,LD_M}<=2'b01;

                 end

              else

                 begin

                   count2<=CHANGE;

                   {LD_H,LD_M}<=2'b10;

                 end

              {count1,count2}<=0;

 

        end

      1:begin if(fm)

                 begin

                   lcount1<=CHANGE;

                   {LD_H,LD_M}<=2'b01;

                 end

              else

                 begin

                   lcount2<=CHANGE;

                   {LD_H,LD_M}<=2'b10;

                 end

              {lcount1,lcount2}<=0;

 

        end

      default:{count1,count2,lcount1,lcount2,LD_H,LD_M}<=0;

     endcase

end

 

always @(posedge CLK_1Hz)  //秒计时和秒调整

  if(!(TSEC^8'h59)|TURN&(!m))

    begin TSEC<=0;

          if(!(TURN&(!m)))

            mclk<=1;

    end

  else begin

     if(TSEC[3:0]==9)

           begin TSEC[3:0]<=0;

                 TSEC[7:4]<=TSEC[7:4]+1;

           end

     else TSEC[3:0]<=TSEC[3:0]+1;

       mclk<=0;

       end

 

assign m_clk=mclk|count1;

assign h_clk=hclk|count2;

assign ct1=CLK|m_clk;    //ct1用于计时、校时中的分钟计数

assign ct2=CLK|h_clk;    //ct2用于计时、校时中的小时计数 

assign lct1=CLK|lcount1; //lct1用于定时状态下调整分钟信号

assign lct2=CLK|lcount2; //lct2用于定时状态下调整小时信号

 

always @(posedge ct1)    //分计时和分调整

  begin if(TMIN==8'h59)

          begin TMIN<=0;

                hclk<=1;

          end

        else begin

          if(TMIN[3:0]==9)

             begin TMIN[3:0]<=0;

                   TMIN[7:4]<=TMIN[7:4]+1;

             end

         else TMIN[3:0]<=TMIN[3:0]+1;

            hclk<=0;

            end

  end

 

always @(posedge ct2)    //小时计时和小时调整

   if(THOU==8'h23)

        THOU<=0;

   else begin

          if(THOU[3:0]==9)

             begin THOU[3:0]<=0;

                 THOU[7:4]<=THOU[7:4]+1;

             end

          else THOU[3:0]<=THOU[3:0]+1;

        end