_primary.vhd

来自「FPGA-CPLD_DesignTool,事例程序陆续上传请需要的朋友下载」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity hdl_demo is
    port(
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        start_value     : in     vl_logic_vector(31 downto 0);
        in_a            : in     vl_logic;
        in_b            : in     vl_logic;
        in_c            : in     vl_logic;
        accum_a         : in     vl_logic_vector(7 downto 0);
        accum_b         : in     vl_logic_vector(7 downto 0);
        result          : out    vl_logic_vector(7 downto 0)
    );
end hdl_demo;