dpram_core_demo.gfl

FPGA-CPLD_DesignTool,事例程序陆续上传请需要的朋友下载

# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
j:\projects\ise\coregendemo\dpram_core_demo/_ngo
top.ngd
top_ngdbuild.nav
top.bld
UCF_Demo.ucf.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top.dly
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.cmd_log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log