📄 ram44.tan.rpt
字号:
; N/A ; None ; -3.600 ns ; add[0] ; ram:inst1|data2[2] ; clk ;
; N/A ; None ; -3.600 ns ; add[0] ; ram:inst1|data0[2] ; clk ;
; N/A ; None ; -3.600 ns ; add[0] ; ram:inst1|data1[3] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data2[0] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data3[1] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data1[1] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data3[2] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data2[2] ; clk ;
; N/A ; None ; -3.600 ns ; add[1] ; ram:inst1|data3[3] ; clk ;
; N/A ; None ; -3.700 ns ; add[0] ; ram:inst1|data3[1] ; clk ;
; N/A ; None ; -3.700 ns ; add[0] ; ram:inst1|data1[1] ; clk ;
; N/A ; None ; -3.700 ns ; add[0] ; ram:inst1|data3[2] ; clk ;
; N/A ; None ; -3.700 ns ; add[0] ; ram:inst1|data3[3] ; clk ;
; N/A ; None ; -4.200 ns ; rd ; ram:inst1|data2[1] ; clk ;
; N/A ; None ; -4.200 ns ; rd ; ram:inst1|data0[1] ; clk ;
; N/A ; None ; -4.200 ns ; rd ; ram:inst1|data2[3] ; clk ;
; N/A ; None ; -4.300 ns ; rd ; ram:inst1|q[1]~reg0 ; clk ;
; N/A ; None ; -4.300 ns ; rd ; ram:inst1|data1[0] ; clk ;
; N/A ; None ; -4.300 ns ; rd ; ram:inst1|data0[0] ; clk ;
; N/A ; None ; -4.300 ns ; rd ; ram:inst1|data0[2] ; clk ;
; N/A ; None ; -4.300 ns ; rd ; ram:inst1|data1[3] ; clk ;
; N/A ; None ; -4.400 ns ; rst ; ram:inst1|q[1]~reg0 ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data2[0] ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data3[1] ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data1[1] ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data3[2] ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data2[2] ; clk ;
; N/A ; None ; -4.400 ns ; rd ; ram:inst1|data3[3] ; clk ;
; N/A ; None ; -4.500 ns ; rd ; ram:inst1|q[3]~reg0 ; clk ;
; N/A ; None ; -4.600 ns ; rst ; ram:inst1|q[3]~reg0 ; clk ;
; N/A ; None ; -4.600 ns ; rd ; ram:inst1|q[0]~reg0 ; clk ;
; N/A ; None ; -4.600 ns ; rd ; ram:inst1|q[2]~reg0 ; clk ;
; N/A ; None ; -4.700 ns ; rst ; ram:inst1|q[0]~reg0 ; clk ;
; N/A ; None ; -4.700 ns ; rst ; ram:inst1|q[2]~reg0 ; clk ;
+---------------+-------------+-----------+---------+---------------------+----------+
+-------------------------------------------------------------------------------------------+
; Minimum tco ;
+--------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+---------------------+----+------------+
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; a ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; b ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; c ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; d ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; e ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; f ; clk ;
; N/A ; None ; 18.800 ns ; ram:inst1|q[3]~reg0 ; g ; clk ;
; N/A ; None ; 18.900 ns ; ram:inst1|q[1]~reg0 ; a ; clk ;
; N/A ; None ; 18.900 ns ; ram:inst1|q[1]~reg0 ; b ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; a ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; b ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; c ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[1]~reg0 ; c ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; d ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[1]~reg0 ; d ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; e ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[1]~reg0 ; e ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; f ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[1]~reg0 ; f ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[2]~reg0 ; g ; clk ;
; N/A ; None ; 19.000 ns ; ram:inst1|q[0]~reg0 ; g ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; a ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; b ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; c ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; d ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; e ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[0]~reg0 ; f ; clk ;
; N/A ; None ; 19.100 ns ; ram:inst1|q[1]~reg0 ; g ; clk ;
+---------------+------------------+----------------+---------------------+----+------------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
Info: Processing started: Mon Jul 26 17:01:31 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off ram44 -c ram44
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 200.0 MHz between source register ram:inst1|data3[3] and destination register ram:inst1|q[3]~reg0
Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 3.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A28; Fanout = 1; REG Node = 'ram:inst1|data3[3]'
Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC5_A28; Fanout = 1; COMB Node = 'ram:inst1|i~666'
Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1|q[3]~reg0'
Info: Total cell delay = 2.600 ns ( 81.25 % )
Info: Total interconnect delay = 0.600 ns ( 18.75 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clk to destination register is 7.500 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1|q[3]~reg0'
Info: Total cell delay = 4.900 ns ( 65.33 % )
Info: Total interconnect delay = 2.600 ns ( 34.67 % )
Info: - Longest clock path from clock clk to source register is 7.500 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC3_A28; Fanout = 1; REG Node = 'ram:inst1|data3[3]'
Info: Total cell delay = 4.900 ns ( 65.33 % )
Info: Total interconnect delay = 2.600 ns ( 34.67 % )
Info: + Micro clock to output delay of source is 0.500 ns
Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register ram:inst1|q[0]~reg0 (data pin = rst, clock pin = clk) is 6.600 ns
Info: + Longest pin to register delay is 13.400 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_97; Fanout = 1; PIN Node = 'rst'
Info: 2: + IC(4.500 ns) + CELL(1.600 ns) = 11.000 ns; Loc. = LC1_A36; Fanout = 4; COMB Node = 'ram:inst1|q[3]~50'
Info: 3: + IC(1.400 ns) + CELL(1.000 ns) = 13.400 ns; Loc. = LC4_A23; Fanout = 7; REG Node = 'ram:inst1|q[0]~reg0'
Info: Total cell delay = 7.500 ns ( 55.97 % )
Info: Total interconnect delay = 5.900 ns ( 44.03 % )
Info: + Micro setup delay of destination is 0.600 ns
Info: - Shortest clock path from clock clk to destination register is 7.400 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC4_A23; Fanout = 7; REG Node = 'ram:inst1|q[0]~reg0'
Info: Total cell delay = 4.900 ns ( 66.22 % )
Info: Total interconnect delay = 2.500 ns ( 33.78 % )
Info: tco from clock clk to destination pin g through register ram:inst1|q[1]~reg0 is 19.100 ns
Info: + Longest clock path from clock clk to source register is 7.500 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC1_A34; Fanout = 7; REG Node = 'ram:inst1|q[1]~reg0'
Info: Total cell delay = 4.900 ns ( 65.33 % )
Info: Total interconnect delay = 2.600 ns ( 34.67 % )
Info: + Micro clock to output delay of source is 0.500 ns
Info: + Longest register to pin delay is 11.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A34; Fanout = 7; REG Node = 'ram:inst1|q[1]~reg0'
Info: 2: + IC(2.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC1_F30; Fanout = 1; COMB Node = 'DELED:inst|DOUT[6]~12'
Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 11.100 ns; Loc. = Pin_137; Fanout = 0; PIN Node = 'g'
Info: Total cell delay = 7.900 ns ( 71.17 % )
Info: Total interconnect delay = 3.200 ns ( 28.83 % )
Info: th for register ram:inst1|data3[1] (data pin = data[1], clock pin = clk) is 0.900 ns
Info: + Longest clock path from clock clk to destination register is 7.500 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC2_A34; Fanout = 1; REG Node = 'ram:inst1|data3[1]'
Info: Total cell delay = 4.900 ns ( 65.33 % )
Info: Total interconnect delay = 2.600 ns ( 34.67 % )
Info: + Micro hold delay of destination is 1.300 ns
Info: - Shortest pin to register delay is 7.900 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_38; Fanout = 4; PIN Node = 'data[1]'
Info: 2: + IC(2.200 ns) + CELL(0.800 ns) = 7.900 ns; Loc. = LC2_A34; Fanout = 1; REG Node = 'ram:inst1|data3[1]'
Info: Total cell delay = 5.700 ns ( 72.15 % )
Info: Total interconnect delay = 2.200 ns ( 27.85 % )
Info: Minimum tco from clock clk to destination pin a through register ram:inst1|q[3]~reg0 is 18.800 ns
Info: + Shortest clock path from clock clk to source register is 7.500 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'
Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1|q[3]~reg0'
Info: Total cell delay = 4.900 ns ( 65.33 % )
Info: Total interconnect delay = 2.600 ns ( 34.67 % )
Info: + Micro clock to output delay of source is 0.500 ns
Info: + Shortest register to pin delay is 10.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1|q[3]~reg0'
Info: 2: + IC(2.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_F36; Fanout = 1; COMB Node = 'DELED:inst|DOUT[0]~0'
Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 10.800 ns; Loc. = Pin_144; Fanout = 0; PIN Node = 'a'
Info: Total cell delay = 7.700 ns ( 71.30 % )
Info: Total interconnect delay = 3.100 ns ( 28.70 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Jul 26 17:01:33 2004
Info: Elapsed time: 00:00:01
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