ram44.map.eqn

此程序为dsp原码程序

--C1L33Q is ram:inst1|q[0]~reg0
--operation mode is normal

C1L33Q_lut_out = C1L62 & (C1L52 # !add[1]) # !C1L62 & C1L52 & add[1];
C1L33Q = DFFEA(C1L33Q_lut_out, clk, , , C1L63, , );


--C1L43Q is ram:inst1|q[1]~reg0
--operation mode is normal

C1L43Q_lut_out = C1L82 & (C1L72 # !add[1]) # !C1L82 & C1L72 & add[1];
C1L43Q = DFFEA(C1L43Q_lut_out, clk, , , C1L63, , );


--C1L53Q is ram:inst1|q[2]~reg0
--operation mode is normal

C1L53Q_lut_out = C1L03 & (C1L92 # !add[1]) # !C1L03 & C1L92 & add[1];
C1L53Q = DFFEA(C1L53Q_lut_out, clk, , , C1L63, , );


--C1L73Q is ram:inst1|q[3]~reg0
--operation mode is normal

C1L73Q_lut_out = C1L23 & (C1L13 # !add[1]) # !C1L23 & C1L13 & add[1];
C1L73Q = DFFEA(C1L73Q_lut_out, clk, , , C1L63, , );


--B1L1 is DELED:inst|DOUT[0]~0
--operation mode is normal

B1L1 = C1L53Q & !C1L43Q & (C1L33Q $ !C1L73Q) # !C1L53Q & C1L33Q & (C1L43Q $ !C1L73Q);


--B1L2 is DELED:inst|DOUT[1]~2
--operation mode is normal

B1L2 = C1L43Q & (C1L33Q & C1L73Q # !C1L33Q & C1L53Q) # !C1L43Q & C1L53Q & (C1L33Q $ C1L73Q);


--B1L3 is DELED:inst|DOUT[2]~4
--operation mode is normal

B1L3 = C1L53Q & C1L73Q & (C1L43Q # !C1L33Q) # !C1L53Q & !C1L33Q & C1L43Q & !C1L73Q;


--B1L4 is DELED:inst|DOUT[3]~6
--operation mode is normal

B1L4 = C1L43Q & (C1L33Q & C1L53Q # !C1L33Q & !C1L53Q & C1L73Q) # !C1L43Q & !C1L73Q & (C1L33Q $ C1L53Q);


--B1L5 is DELED:inst|DOUT[4]~8
--operation mode is normal

B1L5 = C1L43Q & C1L33Q & !C1L73Q # !C1L43Q & (C1L53Q & !C1L73Q # !C1L53Q & C1L33Q);


--B1L6 is DELED:inst|DOUT[5]~10
--operation mode is normal

B1L6 = C1L33Q & (C1L73Q $ (C1L43Q # !C1L53Q)) # !C1L33Q & C1L43Q & !C1L53Q & !C1L73Q;


--B1L7 is DELED:inst|DOUT[6]~12
--operation mode is normal

B1L7 = C1L33Q & (C1L73Q # C1L43Q $ C1L53Q) # !C1L33Q & (C1L43Q # C1L53Q $ C1L73Q);


--C1_data3[0] is ram:inst1|data3[0]
--operation mode is normal

C1_data3[0]_lut_out = data[0];
C1_data3[0] = DFFEA(C1_data3[0]_lut_out, clk, !rst, , C1L42, , );


--C1_data2[0] is ram:inst1|data2[0]
--operation mode is normal

C1_data2[0]_lut_out = data[0];
C1_data2[0] = DFFEA(C1_data2[0]_lut_out, clk, !rst, , C1L81, , );


--C1L52 is ram:inst1|i~660
--operation mode is normal

C1L52 = C1_data3[0] & (C1_data2[0] # add[0]) # !C1_data3[0] & C1_data2[0] & !add[0];


--C1_data1[0] is ram:inst1|data1[0]
--operation mode is normal

C1_data1[0]_lut_out = data[0];
C1_data1[0] = DFFEA(C1_data1[0]_lut_out, clk, !rst, , C1L21, , );


--C1_data0[0] is ram:inst1|data0[0]
--operation mode is normal

C1_data0[0]_lut_out = data[0];
C1_data0[0] = DFFEA(C1_data0[0]_lut_out, clk, !rst, , C1L6, , );


--C1L62 is ram:inst1|i~661
--operation mode is normal

C1L62 = C1_data1[0] & (C1_data0[0] # add[0]) # !C1_data1[0] & C1_data0[0] & !add[0];


--C1L63 is ram:inst1|q[3]~50
--operation mode is normal

C1L63 = rd & !rst & !wr;


--C1_data3[1] is ram:inst1|data3[1]
--operation mode is normal

C1_data3[1]_lut_out = data[1];
C1_data3[1] = DFFEA(C1_data3[1]_lut_out, clk, !rst, , C1L42, , );


--C1_data2[1] is ram:inst1|data2[1]
--operation mode is normal

C1_data2[1]_lut_out = data[1];
C1_data2[1] = DFFEA(C1_data2[1]_lut_out, clk, !rst, , C1L81, , );


--C1L72 is ram:inst1|i~662
--operation mode is normal

C1L72 = C1_data3[1] & (C1_data2[1] # add[0]) # !C1_data3[1] & C1_data2[1] & !add[0];


--C1_data1[1] is ram:inst1|data1[1]
--operation mode is normal

C1_data1[1]_lut_out = data[1];
C1_data1[1] = DFFEA(C1_data1[1]_lut_out, clk, !rst, , C1L21, , );


--C1_data0[1] is ram:inst1|data0[1]
--operation mode is normal

C1_data0[1]_lut_out = data[1];
C1_data0[1] = DFFEA(C1_data0[1]_lut_out, clk, !rst, , C1L6, , );


--C1L82 is ram:inst1|i~663
--operation mode is normal

C1L82 = C1_data1[1] & (C1_data0[1] # add[0]) # !C1_data1[1] & C1_data0[1] & !add[0];


--C1_data3[2] is ram:inst1|data3[2]
--operation mode is normal

C1_data3[2]_lut_out = data[2];
C1_data3[2] = DFFEA(C1_data3[2]_lut_out, clk, !rst, , C1L42, , );


--C1_data2[2] is ram:inst1|data2[2]
--operation mode is normal

C1_data2[2]_lut_out = data[2];
C1_data2[2] = DFFEA(C1_data2[2]_lut_out, clk, !rst, , C1L81, , );


--C1L92 is ram:inst1|i~664
--operation mode is normal

C1L92 = C1_data3[2] & (C1_data2[2] # add[0]) # !C1_data3[2] & C1_data2[2] & !add[0];


--C1_data1[2] is ram:inst1|data1[2]
--operation mode is normal

C1_data1[2]_lut_out = data[2];
C1_data1[2] = DFFEA(C1_data1[2]_lut_out, clk, !rst, , C1L21, , );


--C1_data0[2] is ram:inst1|data0[2]
--operation mode is normal

C1_data0[2]_lut_out = data[2];
C1_data0[2] = DFFEA(C1_data0[2]_lut_out, clk, !rst, , C1L6, , );


--C1L03 is ram:inst1|i~665
--operation mode is normal

C1L03 = C1_data1[2] & (C1_data0[2] # add[0]) # !C1_data1[2] & C1_data0[2] & !add[0];


--C1_data3[3] is ram:inst1|data3[3]
--operation mode is normal

C1_data3[3]_lut_out = data[3];
C1_data3[3] = DFFEA(C1_data3[3]_lut_out, clk, !rst, , C1L42, , );


--C1_data2[3] is ram:inst1|data2[3]
--operation mode is normal

C1_data2[3]_lut_out = data[3];
C1_data2[3] = DFFEA(C1_data2[3]_lut_out, clk, !rst, , C1L81, , );


--C1L13 is ram:inst1|i~666
--operation mode is normal

C1L13 = C1_data3[3] & (C1_data2[3] # add[0]) # !C1_data3[3] & C1_data2[3] & !add[0];


--C1_data1[3] is ram:inst1|data1[3]
--operation mode is normal

C1_data1[3]_lut_out = data[3];
C1_data1[3] = DFFEA(C1_data1[3]_lut_out, clk, !rst, , C1L21, , );


--C1_data0[3] is ram:inst1|data0[3]
--operation mode is normal

C1_data0[3]_lut_out = data[3];
C1_data0[3] = DFFEA(C1_data0[3]_lut_out, clk, !rst, , C1L6, , );


--C1L23 is ram:inst1|i~667
--operation mode is normal

C1L23 = C1_data1[3] & (C1_data0[3] # add[0]) # !C1_data1[3] & C1_data0[3] & !add[0];


--C1L42 is ram:inst1|data3[3]~13
--operation mode is normal

C1L42 = add[0] & add[1] & wr & !rd;


--C1L81 is ram:inst1|data2[3]~14
--operation mode is normal

C1L81 = add[1] & wr & !add[0] & !rd;


--C1L21 is ram:inst1|data1[3]~12
--operation mode is normal

C1L21 = add[0] & wr & !add[1] & !rd;


--C1L6 is ram:inst1|data0[3]~14
--operation mode is normal

C1L6 = wr & !add[0] & !add[1] & !rd;


--add[1] is add[1]
--operation mode is input

add[1] = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--add[0] is add[0]
--operation mode is input

add[0] = INPUT();


--rd is rd
--operation mode is input

rd = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--wr is wr
--operation mode is input

wr = INPUT();


--data[0] is data[0]
--operation mode is input

data[0] = INPUT();


--data[1] is data[1]
--operation mode is input

data[1] = INPUT();


--data[2] is data[2]
--operation mode is input

data[2] = INPUT();


--data[3] is data[3]
--operation mode is input

data[3] = INPUT();


--a is a
--operation mode is output

a = OUTPUT(!B1L1);


--b is b
--operation mode is output

b = OUTPUT(!B1L2);


--c is c
--operation mode is output

c = OUTPUT(!B1L3);


--d is d
--operation mode is output

d = OUTPUT(!B1L4);


--e is e
--operation mode is output

e = OUTPUT(!B1L5);


--f is f
--operation mode is output

f = OUTPUT(!B1L6);


--g is g
--operation mode is output

g = OUTPUT(B1L7);


--h is h
--operation mode is output

h = OUTPUT(GND);


--sm1 is sm1
--operation mode is output

sm1 = OUTPUT(GND);


--sm2 is sm2
--operation mode is output

sm2 = OUTPUT(VCC);


--sm3 is sm3
--operation mode is output

sm3 = OUTPUT(VCC);


--sm4 is sm4
--operation mode is output

sm4 = OUTPUT(VCC);


--sm5 is sm5
--operation mode is output

sm5 = OUTPUT(VCC);


--sm6 is sm6
--operation mode is output

sm6 = OUTPUT(VCC);


--sm7 is sm7
--operation mode is output

sm7 = OUTPUT(VCC);


--sm8 is sm8
--operation mode is output

sm8 = OUTPUT(VCC);