da.tan.rpt

此程序为dsp原码程序

+------------------------------------------------------------+
; tpd                                                        ;
+-------------------------------------------------------------
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+-------+-------------------+-----------------+------+-------+
; N/A   ; None              ; 10.700 ns       ; clk  ; adclk ;
+-------+-------------------+-----------------+------+-------+


+-----------------------------------------------------------------------------------------+
; th                                                                                      ;
+------------------------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From  ; To                         ; To Clock ;
+---------------+-------------+-----------+-------+----------------------------+----------+
; N/A           ; None        ; -5.100 ns ; da[0] ; da7524:inst1|daout[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.100 ns ; da[1] ; da7524:inst1|daout[1]~reg0 ; clk      ;
; N/A           ; None        ; -5.100 ns ; da[2] ; da7524:inst1|daout[2]~reg0 ; clk      ;
; N/A           ; None        ; -5.100 ns ; da[3] ; da7524:inst1|daout[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.500 ns ; da[6] ; da7524:inst1|daout[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.500 ns ; da[7] ; da7524:inst1|daout[7]~reg0 ; clk      ;
; N/A           ; None        ; -6.600 ns ; da[5] ; da7524:inst1|daout[5]~reg0 ; clk      ;
; N/A           ; None        ; -9.100 ns ; da[4] ; da7524:inst1|daout[4]~reg0 ; clk      ;
; N/A           ; None        ; -9.200 ns ; rst   ; da7524:inst1|daout[7]~reg0 ; clk      ;
; N/A           ; None        ; -9.200 ns ; rst   ; da7524:inst1|daout[6]~reg0 ; clk      ;
; N/A           ; None        ; -9.200 ns ; rst   ; da7524:inst1|daout[5]~reg0 ; clk      ;
; N/A           ; None        ; -9.200 ns ; rst   ; da7524:inst1|daout[4]~reg0 ; clk      ;
; N/A           ; None        ; -9.500 ns ; rst   ; da7524:inst1|daout[3]~reg0 ; clk      ;
; N/A           ; None        ; -9.500 ns ; rst   ; da7524:inst1|daout[2]~reg0 ; clk      ;
; N/A           ; None        ; -9.500 ns ; rst   ; da7524:inst1|daout[1]~reg0 ; clk      ;
; N/A           ; None        ; -9.500 ns ; rst   ; da7524:inst1|daout[0]~reg0 ; clk      ;
+---------------+-------------+-----------+-------+----------------------------+----------+


+--------------------------------------------------------------------------------------------------------+
; Minimum tco                                                                                            ;
+---------------------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From                       ; To       ; From Clock ;
+---------------+------------------+----------------+----------------------------+----------+------------+
; N/A           ; None             ; 10.600 ns      ; da7524:inst1|daout[7]~reg0 ; daout[7] ; clk        ;
; N/A           ; None             ; 10.600 ns      ; da7524:inst1|daout[6]~reg0 ; daout[6] ; clk        ;
; N/A           ; None             ; 11.200 ns      ; da7524:inst1|daout[0]~reg0 ; daout[0] ; clk        ;
; N/A           ; None             ; 11.300 ns      ; da7524:inst1|daout[3]~reg0 ; daout[3] ; clk        ;
; N/A           ; None             ; 11.300 ns      ; da7524:inst1|daout[2]~reg0 ; daout[2] ; clk        ;
; N/A           ; None             ; 11.300 ns      ; da7524:inst1|daout[1]~reg0 ; daout[1] ; clk        ;
; N/A           ; None             ; 11.400 ns      ; da7524:inst1|daout[5]~reg0 ; daout[5] ; clk        ;
; N/A           ; None             ; 11.400 ns      ; da7524:inst1|daout[4]~reg0 ; daout[4] ; clk        ;
+---------------+------------------+----------------+----------------------------+----------+------------+


+--------------------------------------------------------------------+
; Minimum tpd                                                        ;
+---------------------------------------------------------------------
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+---------------+-------------------+-----------------+------+-------+
; N/A           ; None              ; 10.700 ns       ; clk  ; adclk ;
+---------------+-------------------+-----------------+------+-------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 30 13:43:49 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off da -c da
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: No valid register-to-register paths exist for clock clk
Info: tsu for register da7524:inst1|daout[3]~reg0 (data pin = rst, clock pin = clk) is 11.400 ns
    Info: + Longest pin to register delay is 13.200 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_99; Fanout = 8; PIN Node = 'rst'
        Info: 2: + IC(5.500 ns) + CELL(1.700 ns) = 12.100 ns; Loc. = LC2_F4; Fanout = 2; COMB Node = 'ad5510:inst|i20~1'
        Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 13.200 ns; Loc. = LC5_F4; Fanout = 1; REG Node = 'da7524:inst1|daout[3]~reg0'
        Info: Total cell delay = 7.400 ns ( 56.06 % )
        Info: Total interconnect delay = 5.800 ns ( 43.94 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock clk to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_F4; Fanout = 1; REG Node = 'da7524:inst1|daout[3]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock clk to destination pin daout[4] through register da7524:inst1|daout[4]~reg0 is 11.400 ns
    Info: + Longest clock path from clock clk to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'da7524:inst1|daout[4]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'da7524:inst1|daout[4]~reg0'
        Info: 2: + IC(2.200 ns) + CELL(6.300 ns) = 8.500 ns; Loc. = Pin_91; Fanout = 0; PIN Node = 'daout[4]'
        Info: Total cell delay = 6.300 ns ( 74.12 % )
        Info: Total interconnect delay = 2.200 ns ( 25.88 % )
Info: Longest tpd from source pin clk to destination pin adclk is 10.700 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
    Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_A6; Fanout = 1; COMB Node = 'adclk~0'
    Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 10.700 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'adclk'
    Info: Total cell delay = 9.700 ns ( 90.65 % )
    Info: Total interconnect delay = 1.000 ns ( 9.35 % )
Info: th for register da7524:inst1|daout[0]~reg0 (data pin = da[0], clock pin = clk) is -5.100 ns
    Info: + Longest clock path from clock clk to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F4; Fanout = 1; REG Node = 'da7524:inst1|daout[0]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 8.800 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_82; Fanout = 1; PIN Node = 'da[0]'
        Info: 2: + IC(1.200 ns) + CELL(1.600 ns) = 7.700 ns; Loc. = LC7_F4; Fanout = 2; COMB Node = 'ad5510:inst|i23~1'
        Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 8.800 ns; Loc. = LC1_F4; Fanout = 1; REG Node = 'da7524:inst1|daout[0]~reg0'
        Info: Total cell delay = 7.300 ns ( 82.95 % )
        Info: Total interconnect delay = 1.500 ns ( 17.05 % )
Info: Minimum tco from clock clk to destination pin daout[7] through register da7524:inst1|daout[7]~reg0 is 10.600 ns
    Info: + Shortest clock path from clock clk to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C13; Fanout = 1; REG Node = 'da7524:inst1|daout[7]~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Shortest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C13; Fanout = 1; REG Node = 'da7524:inst1|daout[7]~reg0'
        Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = Pin_96; Fanout = 0; PIN Node = 'daout[7]'
        Info: Total cell delay = 6.300 ns ( 81.82 % )
        Info: Total interconnect delay = 1.400 ns ( 18.18 % )
Info: Shortest tpd from source pin clk to destination pin adclk is 10.700 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'
    Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_A6; Fanout = 1; COMB Node = 'adclk~0'
    Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 10.700 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'adclk'
    Info: Total cell delay = 9.700 ns ( 90.65 % )
    Info: Total interconnect delay = 1.000 ns ( 9.35 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jul 30 13:43:51 2004
    Info: Elapsed time: 00:00:01