ad5510.vhd

来自「此程序为dsp原码程序」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;

entity ad5510 is
   port(rst:in std_logic;
   clk:in std_logic;
   d:in std_logic_vector(7 downto 0);
   adclk:out std_logic;
   data:out std_logic_vector(7 downto 0));
end;

architecture adctrl of ad5510 is
 signal lock:std_logic;
begin
lock<=clk;
adclk<=clk;
process(lock,rst)
begin
  if rst='0' then data<=(others=>'0');
  elsif lock='0' then
      data<=d;
  end if;
end process;

end;