da.tan.qmsg

此程序为dsp原码程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk daout\[4\] da7524:inst1\|daout\[4\]~reg0 11.400 ns register " "Info: tco from clock clk to destination pin daout\[4\] through register da7524:inst1\|daout\[4\]~reg0 is 11.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns da7524:inst1\|daout\[4\]~reg0 2 REG LC3_C13 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'da7524:inst1\|daout\[4\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "0.400 ns" { clk da7524:inst1|daout[4]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns da7524:inst1\|daout\[4\]~reg0 1 REG LC3_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'da7524:inst1\|daout\[4\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { da7524:inst1|daout[4]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(6.300 ns) 8.500 ns daout\[4\] 2 PIN Pin_91 0 " "Info: 2: + IC(2.200 ns) + CELL(6.300 ns) = 8.500 ns; Loc. = Pin_91; Fanout = 0; PIN Node = 'daout\[4\]'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "8.500 ns" { da7524:inst1|daout[4]~reg0 daout[4] } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 144 640 816 160 "daout\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 74.12 % " "Info: Total cell delay = 6.300 ns ( 74.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 25.88 % " "Info: Total interconnect delay = 2.200 ns ( 25.88 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "8.500 ns" { da7524:inst1|daout[4]~reg0 daout[4] } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[4]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "8.500 ns" { da7524:inst1|daout[4]~reg0 daout[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk adclk 10.700 ns Longest " "Info: Longest tpd from source pin clk to destination pin adclk is 10.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 3.500 ns adclk~0 2 COMB LC1_A6 1 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_A6; Fanout = 1; COMB Node = 'adclk~0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "1.500 ns" { clk adclk~0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 48 464 640 64 "adclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(6.300 ns) 10.700 ns adclk 3 PIN Pin_69 0 " "Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 10.700 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'adclk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.200 ns" { adclk~0 adclk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 48 464 640 64 "adclk" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.700 ns 90.65 % " "Info: Total cell delay = 9.700 ns ( 90.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 9.35 % " "Info: Total interconnect delay = 1.000 ns ( 9.35 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "10.700 ns" { clk adclk~0 adclk } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "da7524:inst1\|daout\[0\]~reg0 da\[0\] clk -5.100 ns register " "Info: th for register da7524:inst1\|daout\[0\]~reg0 (data pin = da\[0\], clock pin = clk) is -5.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns da7524:inst1\|daout\[0\]~reg0 2 REG LC1_F4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F4; Fanout = 1; REG Node = 'da7524:inst1\|daout\[0\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "0.400 ns" { clk da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns da\[0\] 1 PIN Pin_82 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_82; Fanout = 1; PIN Node = 'da\[0\]'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { da[0] } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 176 56 224 192 "da\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 7.700 ns ad5510:inst\|i23~1 2 COMB LC7_F4 2 " "Info: 2: + IC(1.200 ns) + CELL(1.600 ns) = 7.700 ns; Loc. = LC7_F4; Fanout = 2; COMB Node = 'ad5510:inst\|i23~1'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.800 ns" { da[0] ad5510:inst|i23~1 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/ad5510.vhd" "" "" { Text "D:/workspace/dsp-d/chenpin/da/ad5510.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 8.800 ns da7524:inst1\|daout\[0\]~reg0 3 REG LC1_F4 1 " "Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 8.800 ns; Loc. = LC1_F4; Fanout = 1; REG Node = 'da7524:inst1\|daout\[0\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "1.100 ns" { ad5510:inst|i23~1 da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns 82.95 % " "Info: Total cell delay = 7.300 ns ( 82.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 17.05 % " "Info: Total interconnect delay = 1.500 ns ( 17.05 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "8.800 ns" { da[0] ad5510:inst|i23~1 da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "8.800 ns" { da[0] ad5510:inst|i23~1 da7524:inst1|daout[0]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk daout\[7\] da7524:inst1\|daout\[7\]~reg0 10.600 ns register " "Info: Minimum tco from clock clk to destination pin daout\[7\] through register da7524:inst1\|daout\[7\]~reg0 is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns da7524:inst1\|daout\[7\]~reg0 2 REG LC4_C13 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C13; Fanout = 1; REG Node = 'da7524:inst1\|daout\[7\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "0.400 ns" { clk da7524:inst1|daout[7]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[7]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Shortest register pin " "Info: + Shortest register to pin delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns da7524:inst1\|daout\[7\]~reg0 1 REG LC4_C13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C13; Fanout = 1; REG Node = 'da7524:inst1\|daout\[7\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { da7524:inst1|daout[7]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(6.300 ns) 7.700 ns daout\[7\] 2 PIN Pin_96 0 " "Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = Pin_96; Fanout = 0; PIN Node = 'daout\[7\]'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.700 ns" { da7524:inst1|daout[7]~reg0 daout[7] } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 144 640 816 160 "daout\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 81.82 % " "Info: Total cell delay = 6.300 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 18.18 % " "Info: Total interconnect delay = 1.400 ns ( 18.18 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.700 ns" { da7524:inst1|daout[7]~reg0 daout[7] } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[7]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.700 ns" { da7524:inst1|daout[7]~reg0 daout[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk adclk 10.700 ns Shortest " "Info: Shortest tpd from source pin clk to destination pin adclk is 10.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 3.500 ns adclk~0 2 COMB LC1_A6 1 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC1_A6; Fanout = 1; COMB Node = 'adclk~0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "1.500 ns" { clk adclk~0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 48 464 640 64 "adclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(6.300 ns) 10.700 ns adclk 3 PIN Pin_69 0 " "Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 10.700 ns; Loc. = Pin_69; Fanout = 0; PIN Node = 'adclk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.200 ns" { adclk~0 adclk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 48 464 640 64 "adclk" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.700 ns 90.65 % " "Info: Total cell delay = 9.700 ns ( 90.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 9.35 % " "Info: Total interconnect delay = 1.000 ns ( 9.35 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "10.700 ns" { clk adclk~0 adclk } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 30 13:43:51 2004 " "Info: Processing ended: Fri Jul 30 13:43:51 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}