da.tan.qmsg

此程序为dsp原码程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 30 13:43:49 2004 " "Info: Processing started: Fri Jul 30 13:43:49 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off da -c da " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off da -c da" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "da7524:inst1\|daout\[3\]~reg0 rst clk 11.400 ns register " "Info: tsu for register da7524:inst1\|daout\[3\]~reg0 (data pin = rst, clock pin = clk) is 11.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.200 ns + Longest pin register " "Info: + Longest pin to register delay is 13.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns rst 1 PIN Pin_99 8 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_99; Fanout = 8; PIN Node = 'rst'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { rst } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 144 56 224 160 "rst" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(1.700 ns) 12.100 ns ad5510:inst\|i20~1 2 COMB LC2_F4 2 " "Info: 2: + IC(5.500 ns) + CELL(1.700 ns) = 12.100 ns; Loc. = LC2_F4; Fanout = 2; COMB Node = 'ad5510:inst\|i20~1'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "7.200 ns" { rst ad5510:inst|i20~1 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/ad5510.vhd" "" "" { Text "D:/workspace/dsp-d/chenpin/da/ad5510.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 13.200 ns da7524:inst1\|daout\[3\]~reg0 3 REG LC5_F4 1 " "Info: 3: + IC(0.300 ns) + CELL(0.800 ns) = 13.200 ns; Loc. = LC5_F4; Fanout = 1; REG Node = 'da7524:inst1\|daout\[3\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "1.100 ns" { ad5510:inst|i20~1 da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 56.06 % " "Info: Total cell delay = 7.400 ns ( 56.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.800 ns 43.94 % " "Info: Total interconnect delay = 5.800 ns ( 43.94 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "13.200 ns" { rst ad5510:inst|i20~1 da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_125 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 17; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/da/da.bdf" "" "" { Schematic "D:/workspace/dsp-d/da/da.bdf" { { 160 56 224 176 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns da7524:inst1\|daout\[3\]~reg0 2 REG LC5_F4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_F4; Fanout = 1; REG Node = 'da7524:inst1\|daout\[3\]~reg0'" {  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "0.400 ns" { clk da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } } { "d:/workspace/dsp-d/da/da7524.vhd" "" "" { Text "d:/workspace/dsp-d/da/da7524.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "13.200 ns" { rst ad5510:inst|i20~1 da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/chenpin/da/db/da_cmp.qrpt" Compiler "da" "UNKNOWN" "V1" "D:/workspace/dsp-d/chenpin/da/db/da.quartus_db" { Floorplan "" "" "2.400 ns" { clk da7524:inst1|daout[3]~reg0 } "NODE_NAME" } } }  } 0}