📄 add4.tan.rpt
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Timing Analyzer report for add4
Mon Jul 26 10:38:28 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. tpd
5. Minimum tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1K30TC144-3 ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Ignore user-defined clock settings ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+-------------+------+-------+
; Worst-case tpd ; N/A ; None ; 23.100 ns ; CIN ; COUT ;
; Worst-case minimum tpd ; N/A ; None ; 15.900 ns ; B[2] ; BD[2] ;
+------------------------+-------+---------------+-------------+------+-------+
+------------------------------------------------------------+
; tpd ;
+-------------------------------------------------------------
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-------+
; N/A ; None ; 23.100 ns ; CIN ; COUT ;
; N/A ; None ; 21.500 ns ; CIN ; S[2] ;
; N/A ; None ; 21.300 ns ; CIN ; S[1] ;
; N/A ; None ; 21.100 ns ; A[0] ; COUT ;
; N/A ; None ; 21.000 ns ; A[1] ; COUT ;
; N/A ; None ; 20.800 ns ; A[2] ; COUT ;
; N/A ; None ; 20.600 ns ; A[3] ; COUT ;
; N/A ; None ; 20.300 ns ; B[0] ; COUT ;
; N/A ; None ; 20.100 ns ; CIN ; S[0] ;
; N/A ; None ; 20.000 ns ; B[1] ; COUT ;
; N/A ; None ; 20.000 ns ; CIN ; S[3] ;
; N/A ; None ; 19.800 ns ; B[2] ; COUT ;
; N/A ; None ; 19.700 ns ; B[3] ; COUT ;
; N/A ; None ; 19.500 ns ; A[0] ; S[2] ;
; N/A ; None ; 19.400 ns ; A[1] ; S[2] ;
; N/A ; None ; 19.300 ns ; A[0] ; S[1] ;
; N/A ; None ; 18.900 ns ; A[1] ; S[1] ;
; N/A ; None ; 18.900 ns ; A[2] ; S[2] ;
; N/A ; None ; 18.700 ns ; B[0] ; S[2] ;
; N/A ; None ; 18.500 ns ; B[0] ; S[1] ;
; N/A ; None ; 18.400 ns ; B[1] ; S[2] ;
; N/A ; None ; 18.000 ns ; B[1] ; S[1] ;
; N/A ; None ; 18.000 ns ; B[2] ; S[2] ;
; N/A ; None ; 18.000 ns ; A[0] ; S[3] ;
; N/A ; None ; 17.900 ns ; A[1] ; S[3] ;
; N/A ; None ; 17.800 ns ; A[0] ; S[0] ;
; N/A ; None ; 17.700 ns ; A[2] ; S[3] ;
; N/A ; None ; 17.200 ns ; A[3] ; S[3] ;
; N/A ; None ; 17.200 ns ; B[0] ; S[3] ;
; N/A ; None ; 17.100 ns ; A[0] ; AD[0] ;
; N/A ; None ; 17.100 ns ; A[2] ; AD[2] ;
; N/A ; None ; 17.100 ns ; B[0] ; S[0] ;
; N/A ; None ; 16.900 ns ; A[1] ; AD[1] ;
; N/A ; None ; 16.900 ns ; B[1] ; S[3] ;
; N/A ; None ; 16.800 ns ; A[3] ; AD[3] ;
; N/A ; None ; 16.700 ns ; B[2] ; S[3] ;
; N/A ; None ; 16.400 ns ; B[3] ; S[3] ;
; N/A ; None ; 16.300 ns ; B[1] ; BD[1] ;
; N/A ; None ; 16.300 ns ; B[3] ; BD[3] ;
; N/A ; None ; 15.900 ns ; B[0] ; BD[0] ;
; N/A ; None ; 15.900 ns ; B[2] ; BD[2] ;
+-------+-------------------+-----------------+------+-------+
+--------------------------------------------------------------------+
; Minimum tpd ;
+---------------------------------------------------------------------
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+-------+
; N/A ; None ; 15.900 ns ; B[2] ; BD[2] ;
; N/A ; None ; 15.900 ns ; B[0] ; BD[0] ;
; N/A ; None ; 16.300 ns ; B[3] ; BD[3] ;
; N/A ; None ; 16.300 ns ; B[1] ; BD[1] ;
; N/A ; None ; 16.400 ns ; B[3] ; S[3] ;
; N/A ; None ; 16.700 ns ; B[2] ; S[3] ;
; N/A ; None ; 16.800 ns ; A[3] ; AD[3] ;
; N/A ; None ; 16.900 ns ; B[1] ; S[3] ;
; N/A ; None ; 16.900 ns ; A[1] ; AD[1] ;
; N/A ; None ; 17.100 ns ; B[0] ; S[0] ;
; N/A ; None ; 17.100 ns ; A[2] ; AD[2] ;
; N/A ; None ; 17.100 ns ; A[0] ; AD[0] ;
; N/A ; None ; 17.200 ns ; B[0] ; S[3] ;
; N/A ; None ; 17.200 ns ; A[3] ; S[3] ;
; N/A ; None ; 17.700 ns ; A[2] ; S[3] ;
; N/A ; None ; 17.800 ns ; A[0] ; S[0] ;
; N/A ; None ; 17.900 ns ; A[1] ; S[3] ;
; N/A ; None ; 18.000 ns ; A[0] ; S[3] ;
; N/A ; None ; 18.000 ns ; B[2] ; S[2] ;
; N/A ; None ; 18.000 ns ; B[1] ; S[1] ;
; N/A ; None ; 18.400 ns ; B[1] ; S[2] ;
; N/A ; None ; 18.500 ns ; B[0] ; S[1] ;
; N/A ; None ; 18.700 ns ; B[0] ; S[2] ;
; N/A ; None ; 18.900 ns ; A[2] ; S[2] ;
; N/A ; None ; 18.900 ns ; A[1] ; S[1] ;
; N/A ; None ; 19.300 ns ; A[0] ; S[1] ;
; N/A ; None ; 19.400 ns ; A[1] ; S[2] ;
; N/A ; None ; 19.500 ns ; A[0] ; S[2] ;
; N/A ; None ; 19.700 ns ; B[3] ; COUT ;
; N/A ; None ; 19.800 ns ; B[2] ; COUT ;
; N/A ; None ; 20.000 ns ; CIN ; S[3] ;
; N/A ; None ; 20.000 ns ; B[1] ; COUT ;
; N/A ; None ; 20.100 ns ; CIN ; S[0] ;
; N/A ; None ; 20.300 ns ; B[0] ; COUT ;
; N/A ; None ; 20.600 ns ; A[3] ; COUT ;
; N/A ; None ; 20.800 ns ; A[2] ; COUT ;
; N/A ; None ; 21.000 ns ; A[1] ; COUT ;
; N/A ; None ; 21.100 ns ; A[0] ; COUT ;
; N/A ; None ; 21.300 ns ; CIN ; S[1] ;
; N/A ; None ; 21.500 ns ; CIN ; S[2] ;
; N/A ; None ; 23.100 ns ; CIN ; COUT ;
+---------------+-------------------+-----------------+------+-------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version
Info: Processing started: Mon Jul 26 10:38:27 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off add4 -c add4
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin CIN to destination pin COUT is 23.100 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_99; Fanout = 1; PIN Node = 'CIN'
Info: 2: + IC(4.400 ns) + CELL(0.700 ns) = 10.000 ns; Loc. = LC8_C32; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]'
Info: 3: + IC(0.500 ns) + CELL(0.200 ns) = 10.700 ns; Loc. = LC1_C34; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]'
Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 10.900 ns; Loc. = LC2_C34; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]'
Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 11.100 ns; Loc. = LC3_C34; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]'
Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 11.300 ns; Loc. = LC4_C34; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4]'
Info: 7: + IC(0.000 ns) + CELL(1.400 ns) = 12.700 ns; Loc. = LC5_C34; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~66'
Info: 8: + IC(1.300 ns) + CELL(1.400 ns) = 15.400 ns; Loc. = LC3_C25; Fanout = 1; COMB Node = 'COUT~0'
Info: 9: + IC(1.400 ns) + CELL(6.300 ns) = 23.100 ns; Loc. = Pin_13; Fanout = 0; PIN Node = 'COUT'
Info: Total cell delay = 15.500 ns ( 67.10 % )
Info: Total interconnect delay = 7.600 ns ( 32.90 % )
Info: Shortest tpd from source pin B[2] to destination pin BD[2] is 15.900 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_39; Fanout = 3; PIN Node = 'B[2]'
Info: 2: + IC(2.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC6_D34; Fanout = 1; COMB Node = 'BD[2]~1'
Info: 3: + IC(1.200 ns) + CELL(6.300 ns) = 15.900 ns; Loc. = Pin_22; Fanout = 0; PIN Node = 'BD[2]'
Info: Total cell delay = 12.600 ns ( 79.25 % )
Info: Total interconnect delay = 3.300 ns ( 20.75 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jul 26 10:38:28 2004
Info: Elapsed time: 00:00:01
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