📄 ds18b20.src
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; .\ds18b20.SRC generated from: ds18b20.c
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE ds18b20.c BROWSE DEBUG OBJECTEXTEND SRC(.\ds18b20.SRC)
$NOMOD51
NAME DS18B20
P0M1 DATA 084H
P1M1 DATA 091H
P0M2 DATA 085H
P0 DATA 080H
P2M1 DATA 0A4H
P1M2 DATA 092H
P1 DATA 090H
AA BIT 0D8H.2
P3M1 DATA 0B1H
P2M2 DATA 0A5H
P2 DATA 0A0H
P3M2 DATA 0B2H
P3 DATA 0B0H
T0 BIT 090H.2
EI2C BIT 0E8H.0
AC BIT 0D0H.6
T1 BIT 080H.7
EA BIT 0A8H.7
EC BIT 0E8H.2
EWDRT BIT 0A8H.6
SPCTL DATA 0E2H
HLTRN BIT 0C8H.6
HC164_AB BIT 080H.4
FE BIT 098H.7
IEN0 DATA 0A8H
IEN1 DATA 0E8H
RxD BIT 090H.1
I2EN BIT 0D8H.6
TxD BIT 090H.0
SSTAT DATA 0BAH
IP0H DATA 0B7H
CMP1 DATA 0ACH
PWDRT BIT 0B8H.6
IP1H DATA 0F7H
CMP2 DATA 0ADH
TMOD20 BIT 0C8H.0
ES BIT 0A8H.4
TMOD21 BIT 0C8H.1
EIEE BIT 0E8H.7
RI BIT 098H.0
DS18B20_DQ BIT 090H.3
INT0 BIT 090H.3
SI BIT 0D8H.3
EKBI BIT 0E8H.1
CY BIT 0D0H.7
INT1 BIT 090H.4
TI BIT 098H.1
D12_CS BIT 080H.0
WFEED1 DATA 0C2H
WFEED2 DATA 0C3H
ECCU BIT 0E8H.4
PS BIT 0B8H.4
SP DATA 081H
Flash_ALE BIT 080H.7
OV BIT 0D0H.2
Flash_CLE BIT 080H.6
SS BIT 0A0H.4
I2SCLH DATA 0DDH
DEEADR DATA 0F3H
DEEDAT DATA 0F2H
Key BIT 090H.3
I2SCLL DATA 0DCH
DEECON DATA 0F1H
DIVM DATA 095H
SBUF DATA 099H
PCON DATA 087H
ESPI BIT 0E8H.3
RTCH DATA 0D2H
SCON DATA 098H
TPCR2H DATA 0CBH
TMOD DATA 089H
TCON DATA 088H
RTCL DATA 0D3H
MOSI BIT 0A0H.2
MISO BIT 0A0H.3
TPCR2L DATA 0CAH
I2STAT DATA 0D9H
KBMASK DATA 086H
KB0 BIT 080H.0
TRIM DATA 096H
BRGCON DATA 0BDH
KB1 BIT 080H.1
IE0 BIT 088H.1
KB2 BIT 080H.2
IE1 BIT 088H.3
KB3 BIT 080H.3
KB4 BIT 080H.4
B DATA 0F0H
KB5 BIT 080H.5
PB0 BIT 0B8H.5
KBPATN DATA 093H
KB6 BIT 080H.6
KB7 BIT 080H.7
ACC DATA 0E0H
SPICLK BIT 0A0H.5
ET0 BIT 0A8H.1
IP0 DATA 0B8H
ET1 BIT 0A8H.3
TF0 BIT 088H.5
IP1 DATA 0F8H
TF1 BIT 088H.7
RTCCON DATA 0D1H
RB8 BIT 098H.2
TCR20 DATA 0C8H
TH0 DATA 08CH
ICA BIT 0A0H.7
EX0 BIT 0A8H.0
IT0 BIT 088H.0
TCR21 DATA 0F9H
TH1 DATA 08DH
ICB BIT 0A0H.0
TB8 BIT 098H.3
EX1 BIT 0A8H.2
IT1 BIT 088H.2
TH2 DATA 0CDH
P BIT 0D0H.0
SM0 BIT 098H.7
TL0 DATA 08AH
SM1 BIT 098H.6
TL1 DATA 08BH
SM2 BIT 098H.5
TL2 DATA 0CCH
OCA BIT 0A0H.6
I2ADR DATA 0DBH
OCB BIT 090H.6
PT0 BIT 0B8H.1
OCC BIT 090H.7
PT1 BIT 0B8H.3
RS0 BIT 0D0H.3
I2DAT DATA 0DAH
OCD BIT 0A0H.1
EBO BIT 0A8H.5
TR0 BIT 088H.4
RS1 BIT 0D0H.4
TR1 BIT 088H.6
SDA BIT 090H.3
PX0 BIT 0B8H.0
PX1 BIT 0B8H.2
PT0AD DATA 0F6H
I2CON DATA 0D8H
DPH DATA 083H
CCCRA DATA 0EAH
CCCRB DATA 0EBH
BRGR0 DATA 0BEH
CPU_RD BIT 080H.1
CCCRC DATA 0ECH
BRGR1 DATA 0BFH
CCCRD DATA 0EDH
DPL DATA 082H
SPSTAT DATA 0E1H
HC164_CLK BIT 090H.2
SCL BIT 090H.2
RSTSRC DATA 0DFH
Flash_RB BIT 090H.5
ALTAB BIT 0C8H.3
REN BIT 098H.4
TICR2 DATA 0C9H
TDIR2 BIT 0C8H.2
Flash_CS BIT 080H.5
WDL DATA 0C1H
STA BIT 0D8H.5
TISE2 DATA 0DEH
TIFR2 DATA 0E9H
ICRAH DATA 0ABH
ALTCD BIT 0C8H.4
ICRBH DATA 0AFH
ESR BIT 0A8H.4
XTAL1 BIT 0B0H.1
XTAL2 BIT 0B0H.0
EST BIT 0E8H.6
ICRAL DATA 0AAH
SADEN DATA 0B9H
ICRBL DATA 0AEH
OCRAH DATA 0EFH
KBCON DATA 094H
OCRBH DATA 0FBH
SADDR DATA 0A9H
NLEDL BIT 090H.7
TOR2H DATA 0CFH
OCRCH DATA 0FDH
OCRDH DATA 0FFH
CPU_WR BIT 080H.2
PCONA DATA 0B5H
OCRAL DATA 0EEH
AUXR1 DATA 0A2H
OCRBL DATA 0FAH
TOR2L DATA 0CEH
OCRCL DATA 0FCH
PSR BIT 0B8H.4
F0 BIT 0D0H.5
OCRDL DATA 0FEH
NLEDR BIT 090H.6
STO BIT 0D8H.4
F1 BIT 0D0H.1
TAMOD DATA 08FH
D12_A0 BIT 080H.3
RST BIT 090H.5
CRSEL BIT 0D8H.0
PSW DATA 0D0H
HLTEN BIT 0C8H.5
PLLEN BIT 0C8H.7
WDCON DATA 0A7H
SPDAT DATA 0E3H
?PR?DS18B20_Initial?DS18B20 SEGMENT CODE
?PR?_DS18B20_Write?DS18B20 SEGMENT CODE
?PR?DS18B20_Read?DS18B20 SEGMENT CODE
?PR?DS18B20_Start?DS18B20 SEGMENT CODE
?PR?DS18B20_WaitDQ?DS18B20 SEGMENT CODE
?PR?DS18B20_ReadTM?DS18B20 SEGMENT CODE
?DT?DS18B20_ReadTM?DS18B20 SEGMENT DATA OVERLAYABLE
?DT?DS18B20 SEGMENT DATA
EXTRN CODE (?C?IMUL)
PUBLIC ROM64Bit
PUBLIC RealTimeTM
PUBLIC RAM9Byte
PUBLIC DS18B20_ReadTM
PUBLIC DS18B20_WaitDQ
PUBLIC DS18B20_Start
PUBLIC DS18B20_Read
PUBLIC _DS18B20_Write
PUBLIC DS18B20_Initial
RSEG ?DT?DS18B20_ReadTM?DS18B20
?DS18B20_ReadTM?BYTE:
j?549: DS 2
RSEG ?DT?DS18B20
RAM9Byte: DS 9
RealTimeTM: DS 4
ROM64Bit: DS 8
; #include "hardware.h"
;
; UCHAR ROM64Bit[8];
; UCHAR RAM9Byte[9];
;
; RealTM RealTimeTM;
;
; bit DS18B20_Initial(void)
RSEG ?PR?DS18B20_Initial?DS18B20
DS18B20_Initial:
USING 0
; SOURCE LINE # 8
; {
; SOURCE LINE # 9
; UINT i;
;
; DS18B20_DQ=0;
; SOURCE LINE # 12
CLR DS18B20_DQ
; i=400;
; SOURCE LINE # 13
;---- Variable 'i?040' assigned to Register 'R6/R7' ----
MOV R7,#090H
MOV R6,#01H
?C0001:
; while(i--); //delay minimum= 480us
; SOURCE LINE # 14
MOV A,R7
DEC R7
MOV R4,AR6
JNZ ?C0059
DEC R6
?C0059:
ORL A,R4
JNZ ?C0001
?C0002:
; DS18B20_DQ=1;
; SOURCE LINE # 15
SETB DS18B20_DQ
; i=15;
; SOURCE LINE # 16
MOV R6,#00H
MOV R7,#0FH
?C0003:
; while(i--); //delay 15~60us
; SOURCE LINE # 17
MOV A,R7
DEC R7
MOV R4,AR6
JNZ ?C0060
DEC R6
?C0060:
ORL A,R4
JNZ ?C0003
?C0004:
; i=100;
; SOURCE LINE # 18
MOV R6,#00H
MOV R7,#064H
?C0005:
; while(i--) //delay 60~240us
; SOURCE LINE # 19
MOV A,R7
DEC R7
MOV R4,AR6
JNZ ?C0061
DEC R6
?C0061:
ORL A,R4
JZ ?C0006
; if(!DS18B20_DQ)
; SOURCE LINE # 20
JB DS18B20_DQ,?C0005
; break;
; SOURCE LINE # 21
?C0006:
;
; if(i==0xFFFF)
; SOURCE LINE # 23
CJNE R6,#0FFH,?C0008
CJNE R7,#0FFH,?C0008
; return 0;
; SOURCE LINE # 24
CLR C
RET
?C0008:
; i=200; //delay 240us
; SOURCE LINE # 25
MOV R6,#00H
MOV R7,#0C8H
?C0010:
; while(i--);
; SOURCE LINE # 26
MOV A,R7
DEC R7
MOV R4,AR6
JNZ ?C0062
DEC R6
?C0062:
ORL A,R4
JNZ ?C0010
?C0011:
; return 1;
; SOURCE LINE # 27
SETB C
; }
; SOURCE LINE # 28
?C0009:
RET
; END OF DS18B20_Initial
;
; void DS18B20_Write(UCHAR Dat)
RSEG ?PR?_DS18B20_Write?DS18B20
_DS18B20_Write:
USING 0
; SOURCE LINE # 30
;---- Variable 'Dat?141' assigned to Register 'R7' ----
; {
; SOURCE LINE # 31
; UCHAR i=0;
; SOURCE LINE # 32
;---- Variable 'i?142' assigned to Register 'R6' ----
; UCHAR j;
;
; for(j=1;j<=8;j++)
; SOURCE LINE # 35
;---- Variable 'j?143' assigned to Register 'R5' ----
MOV R5,#01H
?C0012:
; {
; SOURCE LINE # 36
; if((Dat&0x01)==0x01)
; SOURCE LINE # 37
MOV A,R7
JNB ACC.0,?C0015
; {
; SOURCE LINE # 38
; DS18B20_DQ=0;
; SOURCE LINE # 39
CLR DS18B20_DQ
; for(i=0;i<5;i++); //delay min=1us
; SOURCE LINE # 40
CLR A
MOV R6,A
?C0016:
INC R6
CJNE R6,#05H,?C0016
?C0017:
; DS18B20_DQ=1;
; SOURCE LINE # 41
SETB DS18B20_DQ
; i=15;
; SOURCE LINE # 42
MOV R6,#0FH
?C0019:
; while(i--); //delay max=60us
; SOURCE LINE # 43
MOV R4,AR6
DEC R6
MOV A,R4
JZ ?C0021
SJMP ?C0019
; }
; SOURCE LINE # 44
?C0015:
; else
; {
; SOURCE LINE # 46
; DS18B20_DQ=0;
; SOURCE LINE # 47
CLR DS18B20_DQ
; i=100; //delay min=60us max=120us
; SOURCE LINE # 48
MOV R6,#064H
?C0022:
; while(i--);
; SOURCE LINE # 49
MOV R4,AR6
DEC R6
MOV A,R4
JNZ ?C0022
?C0023:
; DS18B20_DQ=1;
; SOURCE LINE # 50
SETB DS18B20_DQ
; for(i=0;i<5;i++); //delay min=1us
; SOURCE LINE # 51
CLR A
MOV R6,A
?C0024:
INC R6
CJNE R6,#05H,?C0024
; }
; SOURCE LINE # 52
?C0021:
; Dat>>=1;
; SOURCE LINE # 53
MOV A,R7
CLR C
RRC A
MOV R7,A
; }
; SOURCE LINE # 54
INC R5
CJNE R5,#09H,?C0012
; }
; SOURCE LINE # 55
?C0027:
RET
; END OF _DS18B20_Write
;
; UCHAR DS18B20_Read(void)
RSEG ?PR?DS18B20_Read?DS18B20
DS18B20_Read:
USING 0
; SOURCE LINE # 57
; {
; SOURCE LINE # 58
; UCHAR i,j;
; UCHAR Dat;
;
; Dat=0;
; SOURCE LINE # 62
;---- Variable 'Dat?246' assigned to Register 'R7' ----
CLR A
MOV R7,A
; for(i=0;i<8;i++)
; SOURCE LINE # 63
;---- Variable 'i?244' assigned to Register 'R6' ----
MOV R6,A
?C0028:
; {
; SOURCE LINE # 64
; DS18B20_DQ=0;
; SOURCE LINE # 65
CLR DS18B20_DQ
; for(j=0;j<5;j++); //delay min=1us
; SOURCE LINE # 66
;---- Variable 'j?245' assigned to Register 'R5' ----
CLR A
MOV R5,A
?C0031:
INC R5
CJNE R5,#05H,?C0031
?C0032:
; DS18B20_DQ=1;
; SOURCE LINE # 67
SETB DS18B20_DQ
; for(j=0;j<5;j++); //delay 2us~10us
; SOURCE LINE # 68
CLR A
MOV R5,A
?C0034:
INC R5
CJNE R5,#05H,?C0034
?C0035:
; if(DS18B20_DQ)
; SOURCE LINE # 69
JNB DS18B20_DQ,?C0037
; Dat+=1<<i;
; SOURCE LINE # 70
MOV A,#01H
MOV R0,AR6
INC R0
SJMP ?C0064
?C0063:
CLR C
RLC A
?C0064:
DJNZ R0,?C0063
ADD A,R7
MOV R7,A
?C0037:
; j=90;
; SOURCE LINE # 71
MOV R5,#05AH
?C0038:
; while(j--); //delay min=45us
; SOURCE LINE # 72
MOV R4,AR5
DEC R5
MOV A,R4
JNZ ?C0038
; }
; SOURCE LINE # 73
?C0030:
INC R6
CJNE R6,#08H,?C0028
?C0029:
; return Dat;
; SOURCE LINE # 74
; }
; SOURCE LINE # 75
?C0040:
RET
; END OF DS18B20_Read
;
; UCHAR DS18B20_Start(void)
RSEG ?PR?DS18B20_Start?DS18B20
DS18B20_Start:
USING 0
; SOURCE LINE # 77
; {
; SOURCE LINE # 78
; UCHAR i;
;
; if(!DS18B20_Initial())
; SOURCE LINE # 81
LCALL DS18B20_Initial
JC ?C0041
; return 0;
; SOURCE LINE # 82
MOV R7,#00H
RET
?C0041:
;
; DS18B20_Write(0x33); //read rom code 64bit
; SOURCE LINE # 84
MOV R7,#033H
LCALL _DS18B20_Write
;
; for(i=0;i<8;i++)
; SOURCE LINE # 86
;---- Variable 'i?347' assigned to Register 'R3' ----
CLR A
MOV R3,A
?C0043:
; ROM64Bit[i]=DS18B20_Read();
; SOURCE LINE # 87
LCALL DS18B20_Read
MOV A,#LOW (ROM64Bit)
ADD A,R3
MOV R0,A
MOV @R0,AR7
INC R3
CJNE R3,#08H,?C0043
?C0044:
;
; DS18B20_Write(0x44); //start convert temprature
; SOURCE LINE # 89
MOV R7,#044H
LCALL _DS18B20_Write
;
;
; return 1;
; SOURCE LINE # 92
MOV R7,#01H
; }
; SOURCE LINE # 93
?C0042:
RET
; END OF DS18B20_Start
;
; void DS18B20_WaitDQ(void)
RSEG ?PR?DS18B20_WaitDQ?DS18B20
DS18B20_WaitDQ:
; SOURCE LINE # 95
; {
; SOURCE LINE # 96
?C0046:
; while(!DS18B20_DQ);
; SOURCE LINE # 97
JNB DS18B20_DQ,?C0046
; }
; SOURCE LINE # 98
?C0048:
RET
; END OF DS18B20_WaitDQ
;
; void DS18B20_ReadTM(void)
RSEG ?PR?DS18B20_ReadTM?DS18B20
DS18B20_ReadTM:
USING 0
; SOURCE LINE # 100
; {
; SOURCE LINE # 101
; UCHAR i;
; UINT j;
;
; DS18B20_Initial();
; SOURCE LINE # 105
LCALL DS18B20_Initial
;
; DS18B20_Write(0x33); //read rom code 64bit
; SOURCE LINE # 107
MOV R7,#033H
LCALL _DS18B20_Write
;
; for(i=0;i<8;i++)
; SOURCE LINE # 109
;---- Variable 'i?548' assigned to Register 'R3' ----
CLR A
MOV R3,A
?C0049:
; ROM64Bit[i]=DS18B20_Read();
; SOURCE LINE # 110
LCALL DS18B20_Read
MOV A,#LOW (ROM64Bit)
ADD A,R3
MOV R0,A
MOV @R0,AR7
INC R3
CJNE R3,#08H,?C0049
?C0050:
;
; DS18B20_Write(0xBE); //Read temprature
; SOURCE LINE # 112
MOV R7,#0BEH
LCALL _DS18B20_Write
;
; for(i=0;i<9;i++)
; SOURCE LINE # 114
CLR A
MOV R3,A
?C0052:
; RAM9Byte[i]=DS18B20_Read();
; SOURCE LINE # 115
LCALL DS18B20_Read
MOV A,#LOW (RAM9Byte)
ADD A,R3
MOV R0,A
MOV @R0,AR7
INC R3
CJNE R3,#09H,?C0052
?C0053:
;
; ((UCHAR *)&j)[0]=RAM9Byte[1];
; SOURCE LINE # 117
MOV j?549,RAM9Byte+01H
; ((UCHAR *)&j)[1]=RAM9Byte[0];
; SOURCE LINE # 118
MOV j?549+01H,RAM9Byte
;
; if(RAM9Byte[1]>0x80)
; SOURCE LINE # 120
MOV A,RAM9Byte+01H
SETB C
SUBB A,#080H
JC ?C0055
; {
; SOURCE LINE # 121
; RealTimeTM.Sign=1;
; SOURCE LINE # 122
MOV RealTimeTM,#01H
; RealTimeTM.ZhengShu=(UCHAR)(~j>>4);
; SOURCE LINE # 123
MOV A,j?549+01H
CPL A
MOV R7,A
MOV A,j?549
CPL A
SWAP A
MOV R0,A
ANL A,#0F0H
XCH A,R0
MOV A,R7
SWAP A
ANL A,#0FH
ORL A,R0
MOV RealTimeTM+01H,A
; RealTimeTM.XiaoShu=(16-(j&0x000F))*625;
; SOURCE LINE # 124
MOV A,j?549+01H
ANL A,#0FH
MOV R7,A
MOV A,#010H
SUBB A,R7
MOV R7,A
CLR A
SUBB A,#00H
MOV R6,A
MOV R4,#02H
MOV R5,#071H
LCALL ?C?IMUL
MOV RealTimeTM+02H,R6
MOV RealTimeTM+03H,R7
; if(RealTimeTM.XiaoShu==0)
; SOURCE LINE # 125
MOV A,RealTimeTM+03H
ORL A,RealTimeTM+02H
JNZ ?C0058
; RealTimeTM.ZhengShu++;
; SOURCE LINE # 126
INC RealTimeTM+01H
; }
; SOURCE LINE # 127
RET
?C0055:
; else
; {
; SOURCE LINE # 129
; RealTimeTM.Sign=0;
; SOURCE LINE # 130
CLR A
MOV RealTimeTM,A
; RealTimeTM.ZhengShu=(UCHAR)(j>>4);
; SOURCE LINE # 131
MOV A,j?549
SWAP A
MOV R0,A
ANL A,#0F0H
XCH A,R0
MOV A,j?549+01H
SWAP A
ANL A,#0FH
ORL A,R0
MOV RealTimeTM+01H,A
; RealTimeTM.XiaoShu=(j&0x000F)*625;
; SOURCE LINE # 132
MOV R6,#00H
MOV A,j?549+01H
ANL A,#0FH
MOV R7,A
MOV R4,#02H
MOV R5,#071H
LCALL ?C?IMUL
MOV RealTimeTM+02H,R6
MOV RealTimeTM+03H,R7
; }
; SOURCE LINE # 133
; }
; SOURCE LINE # 134
?C0058:
RET
; END OF DS18B20_ReadTM
END
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