fir_compiler_st.v

fir滤波器

defparam Ur1_n_7_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_8_pp;
ram_lut Ur1_n_8_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[8],sym_res_14_n[8],sym_res_13_n[8],sym_res_12_n[8],sym_res_11_n[8] } ), .wr_en(1'b0),.data_out( lut_val_1_n_8_pp[12:0]) ) ;
defparam Ur1_n_8_pp.device_family = "CYCLONE";
defparam Ur1_n_8_pp.init_file = "fir_compiler_coef_1_inv.hex";
defparam Ur1_n_8_pp.data_width = 13;
defparam Ur1_n_8_pp.addr_width = 5;
defparam Ur1_n_8_pp.depth = 32;
defparam Ur1_n_8_pp.mem_core = "M4K";


// ---- partial product adder tree ----

wire [20:0] lut_0_bit_0_fill;
wire [20:0] lut_0_bit_1_fill;
wire [20:0] lut_0_bit_2_fill;
wire [20:0] lut_0_bit_3_fill;
wire [20:0] lut_0_bit_4_fill;
wire [20:0] lut_0_bit_5_fill;
wire [20:0] lut_0_bit_6_fill;
wire [20:0] lut_0_bit_7_fill;
wire [20:0] lut_0_bit_8_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12], lut_val_0_n_0_pp[12],  lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = {lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12], lut_val_0_n_1_pp[12],  lut_val_0_n_1_pp, 1'd0 };
assign lut_0_bit_2_fill = {lut_val_0_n_2_pp[12], lut_val_0_n_2_pp[12], lut_val_0_n_2_pp[12], lut_val_0_n_2_pp[12], lut_val_0_n_2_pp[12], lut_val_0_n_2_pp[12],  lut_val_0_n_2_pp, 2'd0 };
assign lut_0_bit_3_fill = {lut_val_0_n_3_pp[12], lut_val_0_n_3_pp[12], lut_val_0_n_3_pp[12], lut_val_0_n_3_pp[12], lut_val_0_n_3_pp[12],  lut_val_0_n_3_pp, 3'd0 };
assign lut_0_bit_4_fill = {lut_val_0_n_4_pp[12], lut_val_0_n_4_pp[12], lut_val_0_n_4_pp[12], lut_val_0_n_4_pp[12],  lut_val_0_n_4_pp, 4'd0 };
assign lut_0_bit_5_fill = {lut_val_0_n_5_pp[12], lut_val_0_n_5_pp[12], lut_val_0_n_5_pp[12],  lut_val_0_n_5_pp, 5'd0 };
assign lut_0_bit_6_fill = {lut_val_0_n_6_pp[12], lut_val_0_n_6_pp[12],  lut_val_0_n_6_pp, 6'd0 };
assign lut_0_bit_7_fill = {lut_val_0_n_7_pp[12],  lut_val_0_n_7_pp, 7'd0 };
assign lut_0_bit_8_fill = { lut_val_0_n_8_pp, 8'd0 };
wire [21:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 2;
wire [21:0] tree_0_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_2_fill), .bin(lut_0_bit_3_fill), .res(tree_0_pp_l_0_n_1_n) );
defparam Uadd_0_lut_l_0_n_1_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_0_n_1_n.PIPE_DEPTH = 2;
wire [21:0] tree_0_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_4_fill), .bin(lut_0_bit_5_fill), .res(tree_0_pp_l_0_n_2_n) );
defparam Uadd_0_lut_l_0_n_2_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_0_n_2_n.PIPE_DEPTH = 2;
wire [21:0] tree_0_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_3_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_6_fill), .bin(lut_0_bit_7_fill), .res(tree_0_pp_l_0_n_3_n) );
defparam Uadd_0_lut_l_0_n_3_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_0_n_3_n.PIPE_DEPTH = 2;
wire [21:0] tree_0_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_4_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_8_fill), .bin(21'd0), .res(tree_0_pp_l_0_n_4_n) );
defparam Uadd_0_lut_l_0_n_4_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_0_n_4_n.PIPE_DEPTH = 2;

wire [22:0] tree_0_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_0_n), .bin(tree_0_pp_l_0_n_1_n), .res(tree_0_pp_l_1_n_0_n) );
defparam Uadd_0_lut_l_1_n_0_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_1_n_0_n.PIPE_DEPTH = 2;
wire [22:0] tree_0_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_2_n), .bin(tree_0_pp_l_0_n_3_n), .res(tree_0_pp_l_1_n_1_n) );
defparam Uadd_0_lut_l_1_n_1_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_1_n_1_n.PIPE_DEPTH = 2;
wire [22:0] tree_0_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_4_n), .bin(22'd0), .res(tree_0_pp_l_1_n_2_n) );
defparam Uadd_0_lut_l_1_n_2_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_1_n_2_n.PIPE_DEPTH = 2;

wire [23:0] tree_0_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_0_n), .bin(tree_0_pp_l_1_n_1_n), .res(tree_0_pp_l_2_n_0_n) );
defparam Uadd_0_lut_l_2_n_0_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_2_n_0_n.PIPE_DEPTH = 2;
wire [23:0] tree_0_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_2_n), .bin(23'd0), .res(tree_0_pp_l_2_n_1_n) );
defparam Uadd_0_lut_l_2_n_1_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_2_n_1_n.PIPE_DEPTH = 2;

wire [24:0] tree_0_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_3_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_2_n_0_n), .bin(tree_0_pp_l_2_n_1_n), .res(tree_0_pp_l_3_n_0_n) );
defparam Uadd_0_lut_l_3_n_0_n.IN_WIDTH = 24;
defparam Uadd_0_lut_l_3_n_0_n.PIPE_DEPTH = 2;

wire [24:0] lut_val_0_n;
assign lut_val_0_n=tree_0_pp_l_3_n_0_n;


// ---- partial product adder tree ----

wire [20:0] lut_1_bit_0_fill;
wire [20:0] lut_1_bit_1_fill;
wire [20:0] lut_1_bit_2_fill;
wire [20:0] lut_1_bit_3_fill;
wire [20:0] lut_1_bit_4_fill;
wire [20:0] lut_1_bit_5_fill;
wire [20:0] lut_1_bit_6_fill;
wire [20:0] lut_1_bit_7_fill;
wire [20:0] lut_1_bit_8_fill;
assign lut_1_bit_0_fill = {lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12], lut_val_1_n_0_pp[12],  lut_val_1_n_0_pp };
assign lut_1_bit_1_fill = {lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12], lut_val_1_n_1_pp[12],  lut_val_1_n_1_pp, 1'd0 };
assign lut_1_bit_2_fill = {lut_val_1_n_2_pp[12], lut_val_1_n_2_pp[12], lut_val_1_n_2_pp[12], lut_val_1_n_2_pp[12], lut_val_1_n_2_pp[12], lut_val_1_n_2_pp[12],  lut_val_1_n_2_pp, 2'd0 };
assign lut_1_bit_3_fill = {lut_val_1_n_3_pp[12], lut_val_1_n_3_pp[12], lut_val_1_n_3_pp[12], lut_val_1_n_3_pp[12], lut_val_1_n_3_pp[12],  lut_val_1_n_3_pp, 3'd0 };
assign lut_1_bit_4_fill = {lut_val_1_n_4_pp[12], lut_val_1_n_4_pp[12], lut_val_1_n_4_pp[12], lut_val_1_n_4_pp[12],  lut_val_1_n_4_pp, 4'd0 };
assign lut_1_bit_5_fill = {lut_val_1_n_5_pp[12], lut_val_1_n_5_pp[12], lut_val_1_n_5_pp[12],  lut_val_1_n_5_pp, 5'd0 };
assign lut_1_bit_6_fill = {lut_val_1_n_6_pp[12], lut_val_1_n_6_pp[12],  lut_val_1_n_6_pp, 6'd0 };
assign lut_1_bit_7_fill = {lut_val_1_n_7_pp[12],  lut_val_1_n_7_pp, 7'd0 };
assign lut_1_bit_8_fill = { lut_val_1_n_8_pp, 8'd0 };
wire [21:0] tree_1_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_0_fill), .bin(lut_1_bit_1_fill), .res(tree_1_pp_l_0_n_0_n) );
defparam Uadd_1_lut_l_0_n_0_n.IN_WIDTH = 21;
defparam Uadd_1_lut_l_0_n_0_n.PIPE_DEPTH = 2;
wire [21:0] tree_1_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_2_fill), .bin(lut_1_bit_3_fill), .res(tree_1_pp_l_0_n_1_n) );
defparam Uadd_1_lut_l_0_n_1_n.IN_WIDTH = 21;
defparam Uadd_1_lut_l_0_n_1_n.PIPE_DEPTH = 2;
wire [21:0] tree_1_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_4_fill), .bin(lut_1_bit_5_fill), .res(tree_1_pp_l_0_n_2_n) );
defparam Uadd_1_lut_l_0_n_2_n.IN_WIDTH = 21;
defparam Uadd_1_lut_l_0_n_2_n.PIPE_DEPTH = 2;
wire [21:0] tree_1_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_3_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_6_fill), .bin(lut_1_bit_7_fill), .res(tree_1_pp_l_0_n_3_n) );
defparam Uadd_1_lut_l_0_n_3_n.IN_WIDTH = 21;
defparam Uadd_1_lut_l_0_n_3_n.PIPE_DEPTH = 2;
wire [21:0] tree_1_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_4_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_8_fill), .bin(21'd0), .res(tree_1_pp_l_0_n_4_n) );
defparam Uadd_1_lut_l_0_n_4_n.IN_WIDTH = 21;
defparam Uadd_1_lut_l_0_n_4_n.PIPE_DEPTH = 2;

wire [22:0] tree_1_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_0_n), .bin(tree_1_pp_l_0_n_1_n), .res(tree_1_pp_l_1_n_0_n) );
defparam Uadd_1_lut_l_1_n_0_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_1_n_0_n.PIPE_DEPTH = 2;
wire [22:0] tree_1_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_2_n), .bin(tree_1_pp_l_0_n_3_n), .res(tree_1_pp_l_1_n_1_n) );
defparam Uadd_1_lut_l_1_n_1_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_1_n_1_n.PIPE_DEPTH = 2;
wire [22:0] tree_1_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_1_lut_l_1_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_0_n_4_n), .bin(22'd0), .res(tree_1_pp_l_1_n_2_n) );
defparam Uadd_1_lut_l_1_n_2_n.IN_WIDTH = 22;
defparam Uadd_1_lut_l_1_n_2_n.PIPE_DEPTH = 2;

wire [23:0] tree_1_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_0_n), .bin(tree_1_pp_l_1_n_1_n), .res(tree_1_pp_l_2_n_0_n) );
defparam Uadd_1_lut_l_2_n_0_n.IN_WIDTH = 23;
defparam Uadd_1_lut_l_2_n_0_n.PIPE_DEPTH = 2;
wire [23:0] tree_1_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_1_lut_l_2_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_1_n_2_n), .bin(23'd0), .res(tree_1_pp_l_2_n_1_n) );
defparam Uadd_1_lut_l_2_n_1_n.IN_WIDTH = 23;
defparam Uadd_1_lut_l_2_n_1_n.PIPE_DEPTH = 2;

wire [24:0] tree_1_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_3_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_1_pp_l_2_n_0_n), .bin(tree_1_pp_l_2_n_1_n), .res(tree_1_pp_l_3_n_0_n) );
defparam Uadd_1_lut_l_3_n_0_n.IN_WIDTH = 24;
defparam Uadd_1_lut_l_3_n_0_n.PIPE_DEPTH = 2;

wire [24:0] lut_val_1_n;
assign lut_val_1_n=tree_1_pp_l_3_n_0_n;


// ---- final adder tree ----

wire [25:0] fin_atree_l_0_n_0_n;
sadd_lpm_cen Uadd_cen_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_val_0_n), .bin(lut_val_1_n), .res(fin_atree_l_0_n_0_n) );
defparam Uadd_cen_l_0_n_0_n.IN_WIDTH = 25;
defparam Uadd_cen_l_0_n_0_n.PIPE_DEPTH = 2;

wire [25:0] mac_res;
assign mac_res=fin_atree_l_0_n_0_n;
wire [25:0] atree_res;
mac_tl Umtl (.clk(clk), 
             .data_in(mac_res),
             .data_out(atree_res));
defparam Umtl.DATA_WIDTH = 26;

// ---- Adder Tree Complete ---- 
wire [20:0] fir_int_res;
assign fir_int_res = atree_res [20:0];

assign fir_result = fir_int_res[ACCUM_WIDTH-1:0];
wire pre_rdy;
assign rdy_to_ld = pre_rdy;
assign done = done_int;
par_ctrl Uctrl(.rst(rst),
		.clk(clk),
		.clk_en(clk_en),
		.done(done_int),
		.rdy_int(rdy_int),
		.rdy_to_ld(pre_rdy));
defparam Uctrl.REG_LEN = 14;
defparam Uctrl.REG_BIT = 4;
defparam Uctrl.CH_WIDTH =0; 
defparam Uctrl.NUM_CH =1; 
endmodule