fir_compiler_st.v

fir滤波器

wire [8:0] sym_res_9_n;
sadd U_9_sym_add (.clk(clk), .ain(tdl_9_n), .bin(tdl_22_n), .res(sym_res_9_n) );
defparam U_9_sym_add.IN_WIDTH = 8;
defparam U_9_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_10_n;
sadd U_10_sym_add (.clk(clk), .ain(tdl_10_n), .bin(tdl_21_n), .res(sym_res_10_n) );
defparam U_10_sym_add.IN_WIDTH = 8;
defparam U_10_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_11_n;
sadd U_11_sym_add (.clk(clk), .ain(tdl_11_n), .bin(tdl_20_n), .res(sym_res_11_n) );
defparam U_11_sym_add.IN_WIDTH = 8;
defparam U_11_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_12_n;
sadd U_12_sym_add (.clk(clk), .ain(tdl_12_n), .bin(tdl_19_n), .res(sym_res_12_n) );
defparam U_12_sym_add.IN_WIDTH = 8;
defparam U_12_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_13_n;
sadd U_13_sym_add (.clk(clk), .ain(tdl_13_n), .bin(tdl_18_n), .res(sym_res_13_n) );
defparam U_13_sym_add.IN_WIDTH = 8;
defparam U_13_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_14_n;
sadd U_14_sym_add (.clk(clk), .ain(tdl_14_n), .bin(tdl_17_n), .res(sym_res_14_n) );
defparam U_14_sym_add.IN_WIDTH = 8;
defparam U_14_sym_add.PIPE_DEPTH = 1;
wire [8:0] sym_res_15_n;
sadd U_15_sym_add (.clk(clk), .ain(tdl_15_n), .bin(tdl_16_n), .res(sym_res_15_n) );
defparam U_15_sym_add.IN_WIDTH = 8;
defparam U_15_sym_add.PIPE_DEPTH = 1;


wire [12:0] lut_val_0_n_0_pp;
ram_lut Ur0_n_0_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[0],sym_res_9_n[0],sym_res_8_n[0],sym_res_7_n[0],sym_res_6_n[0],sym_res_5_n[0],sym_res_3_n[0],sym_res_2_n[0] } ), .wr_en(1'b0),.data_out( lut_val_0_n_0_pp[9:0]) ) ;
defparam Ur0_n_0_pp.device_family = "CYCLONE";
defparam Ur0_n_0_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_0_pp.data_width = 10;
defparam Ur0_n_0_pp.addr_width = 8;
defparam Ur0_n_0_pp.depth = 256;
defparam Ur0_n_0_pp.mem_core = "M4K";
assign lut_val_0_n_0_pp[12] = lut_val_0_n_0_pp[9];
assign lut_val_0_n_0_pp[11] = lut_val_0_n_0_pp[9];
assign lut_val_0_n_0_pp[10] = lut_val_0_n_0_pp[9];
wire [12:0] lut_val_0_n_1_pp;
ram_lut Ur0_n_1_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[1],sym_res_9_n[1],sym_res_8_n[1],sym_res_7_n[1],sym_res_6_n[1],sym_res_5_n[1],sym_res_3_n[1],sym_res_2_n[1] } ), .wr_en(1'b0),.data_out( lut_val_0_n_1_pp[9:0]) ) ;
defparam Ur0_n_1_pp.device_family = "CYCLONE";
defparam Ur0_n_1_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_1_pp.data_width = 10;
defparam Ur0_n_1_pp.addr_width = 8;
defparam Ur0_n_1_pp.depth = 256;
defparam Ur0_n_1_pp.mem_core = "M4K";
assign lut_val_0_n_1_pp[12] = lut_val_0_n_1_pp[9];
assign lut_val_0_n_1_pp[11] = lut_val_0_n_1_pp[9];
assign lut_val_0_n_1_pp[10] = lut_val_0_n_1_pp[9];
wire [12:0] lut_val_0_n_2_pp;
ram_lut Ur0_n_2_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[2],sym_res_9_n[2],sym_res_8_n[2],sym_res_7_n[2],sym_res_6_n[2],sym_res_5_n[2],sym_res_3_n[2],sym_res_2_n[2] } ), .wr_en(1'b0),.data_out( lut_val_0_n_2_pp[9:0]) ) ;
defparam Ur0_n_2_pp.device_family = "CYCLONE";
defparam Ur0_n_2_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_2_pp.data_width = 10;
defparam Ur0_n_2_pp.addr_width = 8;
defparam Ur0_n_2_pp.depth = 256;
defparam Ur0_n_2_pp.mem_core = "M4K";
assign lut_val_0_n_2_pp[12] = lut_val_0_n_2_pp[9];
assign lut_val_0_n_2_pp[11] = lut_val_0_n_2_pp[9];
assign lut_val_0_n_2_pp[10] = lut_val_0_n_2_pp[9];
wire [12:0] lut_val_0_n_3_pp;
ram_lut Ur0_n_3_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[3],sym_res_9_n[3],sym_res_8_n[3],sym_res_7_n[3],sym_res_6_n[3],sym_res_5_n[3],sym_res_3_n[3],sym_res_2_n[3] } ), .wr_en(1'b0),.data_out( lut_val_0_n_3_pp[9:0]) ) ;
defparam Ur0_n_3_pp.device_family = "CYCLONE";
defparam Ur0_n_3_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_3_pp.data_width = 10;
defparam Ur0_n_3_pp.addr_width = 8;
defparam Ur0_n_3_pp.depth = 256;
defparam Ur0_n_3_pp.mem_core = "M4K";
assign lut_val_0_n_3_pp[12] = lut_val_0_n_3_pp[9];
assign lut_val_0_n_3_pp[11] = lut_val_0_n_3_pp[9];
assign lut_val_0_n_3_pp[10] = lut_val_0_n_3_pp[9];
wire [12:0] lut_val_0_n_4_pp;
ram_lut Ur0_n_4_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[4],sym_res_9_n[4],sym_res_8_n[4],sym_res_7_n[4],sym_res_6_n[4],sym_res_5_n[4],sym_res_3_n[4],sym_res_2_n[4] } ), .wr_en(1'b0),.data_out( lut_val_0_n_4_pp[9:0]) ) ;
defparam Ur0_n_4_pp.device_family = "CYCLONE";
defparam Ur0_n_4_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_4_pp.data_width = 10;
defparam Ur0_n_4_pp.addr_width = 8;
defparam Ur0_n_4_pp.depth = 256;
defparam Ur0_n_4_pp.mem_core = "M4K";
assign lut_val_0_n_4_pp[12] = lut_val_0_n_4_pp[9];
assign lut_val_0_n_4_pp[11] = lut_val_0_n_4_pp[9];
assign lut_val_0_n_4_pp[10] = lut_val_0_n_4_pp[9];
wire [12:0] lut_val_0_n_5_pp;
ram_lut Ur0_n_5_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[5],sym_res_9_n[5],sym_res_8_n[5],sym_res_7_n[5],sym_res_6_n[5],sym_res_5_n[5],sym_res_3_n[5],sym_res_2_n[5] } ), .wr_en(1'b0),.data_out( lut_val_0_n_5_pp[9:0]) ) ;
defparam Ur0_n_5_pp.device_family = "CYCLONE";
defparam Ur0_n_5_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_5_pp.data_width = 10;
defparam Ur0_n_5_pp.addr_width = 8;
defparam Ur0_n_5_pp.depth = 256;
defparam Ur0_n_5_pp.mem_core = "M4K";
assign lut_val_0_n_5_pp[12] = lut_val_0_n_5_pp[9];
assign lut_val_0_n_5_pp[11] = lut_val_0_n_5_pp[9];
assign lut_val_0_n_5_pp[10] = lut_val_0_n_5_pp[9];
wire [12:0] lut_val_0_n_6_pp;
ram_lut Ur0_n_6_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[6],sym_res_9_n[6],sym_res_8_n[6],sym_res_7_n[6],sym_res_6_n[6],sym_res_5_n[6],sym_res_3_n[6],sym_res_2_n[6] } ), .wr_en(1'b0),.data_out( lut_val_0_n_6_pp[9:0]) ) ;
defparam Ur0_n_6_pp.device_family = "CYCLONE";
defparam Ur0_n_6_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_6_pp.data_width = 10;
defparam Ur0_n_6_pp.addr_width = 8;
defparam Ur0_n_6_pp.depth = 256;
defparam Ur0_n_6_pp.mem_core = "M4K";
assign lut_val_0_n_6_pp[12] = lut_val_0_n_6_pp[9];
assign lut_val_0_n_6_pp[11] = lut_val_0_n_6_pp[9];
assign lut_val_0_n_6_pp[10] = lut_val_0_n_6_pp[9];
wire [12:0] lut_val_0_n_7_pp;
ram_lut Ur0_n_7_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[7],sym_res_9_n[7],sym_res_8_n[7],sym_res_7_n[7],sym_res_6_n[7],sym_res_5_n[7],sym_res_3_n[7],sym_res_2_n[7] } ), .wr_en(1'b0),.data_out( lut_val_0_n_7_pp[9:0]) ) ;
defparam Ur0_n_7_pp.device_family = "CYCLONE";
defparam Ur0_n_7_pp.init_file = "fir_compiler_coef_0.hex";
defparam Ur0_n_7_pp.data_width = 10;
defparam Ur0_n_7_pp.addr_width = 8;
defparam Ur0_n_7_pp.depth = 256;
defparam Ur0_n_7_pp.mem_core = "M4K";
assign lut_val_0_n_7_pp[12] = lut_val_0_n_7_pp[9];
assign lut_val_0_n_7_pp[11] = lut_val_0_n_7_pp[9];
assign lut_val_0_n_7_pp[10] = lut_val_0_n_7_pp[9];
wire [12:0] lut_val_0_n_8_pp;
ram_lut Ur0_n_8_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_10_n[8],sym_res_9_n[8],sym_res_8_n[8],sym_res_7_n[8],sym_res_6_n[8],sym_res_5_n[8],sym_res_3_n[8],sym_res_2_n[8] } ), .wr_en(1'b0),.data_out( lut_val_0_n_8_pp[9:0]) ) ;
defparam Ur0_n_8_pp.device_family = "CYCLONE";
defparam Ur0_n_8_pp.init_file = "fir_compiler_coef_0_inv.hex";
defparam Ur0_n_8_pp.data_width = 10;
defparam Ur0_n_8_pp.addr_width = 8;
defparam Ur0_n_8_pp.depth = 256;
defparam Ur0_n_8_pp.mem_core = "M4K";
assign lut_val_0_n_8_pp[12] = lut_val_0_n_8_pp[9];
assign lut_val_0_n_8_pp[11] = lut_val_0_n_8_pp[9];
assign lut_val_0_n_8_pp[10] = lut_val_0_n_8_pp[9];
wire [12:0] lut_val_1_n_0_pp;
ram_lut Ur1_n_0_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[0],sym_res_14_n[0],sym_res_13_n[0],sym_res_12_n[0],sym_res_11_n[0] } ), .wr_en(1'b0),.data_out( lut_val_1_n_0_pp[12:0]) ) ;
defparam Ur1_n_0_pp.device_family = "CYCLONE";
defparam Ur1_n_0_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_0_pp.data_width = 13;
defparam Ur1_n_0_pp.addr_width = 5;
defparam Ur1_n_0_pp.depth = 32;
defparam Ur1_n_0_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_1_pp;
ram_lut Ur1_n_1_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[1],sym_res_14_n[1],sym_res_13_n[1],sym_res_12_n[1],sym_res_11_n[1] } ), .wr_en(1'b0),.data_out( lut_val_1_n_1_pp[12:0]) ) ;
defparam Ur1_n_1_pp.device_family = "CYCLONE";
defparam Ur1_n_1_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_1_pp.data_width = 13;
defparam Ur1_n_1_pp.addr_width = 5;
defparam Ur1_n_1_pp.depth = 32;
defparam Ur1_n_1_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_2_pp;
ram_lut Ur1_n_2_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[2],sym_res_14_n[2],sym_res_13_n[2],sym_res_12_n[2],sym_res_11_n[2] } ), .wr_en(1'b0),.data_out( lut_val_1_n_2_pp[12:0]) ) ;
defparam Ur1_n_2_pp.device_family = "CYCLONE";
defparam Ur1_n_2_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_2_pp.data_width = 13;
defparam Ur1_n_2_pp.addr_width = 5;
defparam Ur1_n_2_pp.depth = 32;
defparam Ur1_n_2_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_3_pp;
ram_lut Ur1_n_3_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[3],sym_res_14_n[3],sym_res_13_n[3],sym_res_12_n[3],sym_res_11_n[3] } ), .wr_en(1'b0),.data_out( lut_val_1_n_3_pp[12:0]) ) ;
defparam Ur1_n_3_pp.device_family = "CYCLONE";
defparam Ur1_n_3_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_3_pp.data_width = 13;
defparam Ur1_n_3_pp.addr_width = 5;
defparam Ur1_n_3_pp.depth = 32;
defparam Ur1_n_3_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_4_pp;
ram_lut Ur1_n_4_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[4],sym_res_14_n[4],sym_res_13_n[4],sym_res_12_n[4],sym_res_11_n[4] } ), .wr_en(1'b0),.data_out( lut_val_1_n_4_pp[12:0]) ) ;
defparam Ur1_n_4_pp.device_family = "CYCLONE";
defparam Ur1_n_4_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_4_pp.data_width = 13;
defparam Ur1_n_4_pp.addr_width = 5;
defparam Ur1_n_4_pp.depth = 32;
defparam Ur1_n_4_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_5_pp;
ram_lut Ur1_n_5_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[5],sym_res_14_n[5],sym_res_13_n[5],sym_res_12_n[5],sym_res_11_n[5] } ), .wr_en(1'b0),.data_out( lut_val_1_n_5_pp[12:0]) ) ;
defparam Ur1_n_5_pp.device_family = "CYCLONE";
defparam Ur1_n_5_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_5_pp.data_width = 13;
defparam Ur1_n_5_pp.addr_width = 5;
defparam Ur1_n_5_pp.depth = 32;
defparam Ur1_n_5_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_6_pp;
ram_lut Ur1_n_6_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[6],sym_res_14_n[6],sym_res_13_n[6],sym_res_12_n[6],sym_res_11_n[6] } ), .wr_en(1'b0),.data_out( lut_val_1_n_6_pp[12:0]) ) ;
defparam Ur1_n_6_pp.device_family = "CYCLONE";
defparam Ur1_n_6_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_6_pp.data_width = 13;
defparam Ur1_n_6_pp.addr_width = 5;
defparam Ur1_n_6_pp.depth = 32;
defparam Ur1_n_6_pp.mem_core = "M4K";
wire [12:0] lut_val_1_n_7_pp;
ram_lut Ur1_n_7_pp(.clk_in(clk), .clk_out(clk), .addr_in( {sym_res_15_n[7],sym_res_14_n[7],sym_res_13_n[7],sym_res_12_n[7],sym_res_11_n[7] } ), .wr_en(1'b0),.data_out( lut_val_1_n_7_pp[12:0]) ) ;
defparam Ur1_n_7_pp.device_family = "CYCLONE";
defparam Ur1_n_7_pp.init_file = "fir_compiler_coef_1.hex";
defparam Ur1_n_7_pp.data_width = 13;
defparam Ur1_n_7_pp.addr_width = 5;
defparam Ur1_n_7_pp.depth = 32;