fir32.mdl

fir滤波器

    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      UnitDelay
      X0		      "0"
      SampleTime	      "1"
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "fir32"
    Location		    [2, 82, 997, 721]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Sum
      Name		      "Add"
      Ports		      [2, 1]
      Position		      [265, 179, 330, 226]
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      OutScaling	      "2^-10"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Reference
      Name		      "Input"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [270, 402, 335, 418]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Input"
      ppat		      "c:\\dsp_biulder_demo\\fir_core\\DSPBuilder_fir3"
"2"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Output"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [815, 432, 880, 448]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "10"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "P1"
      Ports		      [1]
      Position		      [925, 395, 955, 425]
      SourceBlock	      "simulink_extras/Additional\nSinks/Power Spectra"
"l\nDensity"
      SourceType	      "Power Spectral Density"
      ShowPortLabels	      on
      npts		      "256"
      fftpts		      "1024"
      HowOften		      "64"
      sampleT		      "8"
    }
    Block {
      BlockType		      Reference
      Name		      "P2"
      Ports		      [1]
      Position		      [785, 240, 815, 270]
      SourceBlock	      "simulink_extras/Additional\nSinks/Power Spectra"
"l\nDensity"
      SourceType	      "Power Spectral Density"
      ShowPortLabels	      on
      npts		      "256"
      fftpts		      "1024"
      HowOften		      "64"
      sampleT		      "8"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      Name		      "Pulse\nGenerator1"
      Ports		      [0, 1]
      Position		      [750, 39, 850, 111]
      Amplitude		      "100"
      Period		      "100"
      PulseWidth	      "50"
      SampleTime	      "5"
    }
    Block {
      BlockType		      RandomNumber
      Name		      "Random\nNumber"
      Position		      [15, 491, 85, 559]
      Variance		      "50"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Rou5"
      Ports		      [1, 1]
      Position		      [700, 428, 785, 452]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Round"
      SourceType	      "HDLEntity AlteraBlockSet"
      BusType		      "Signed Integer"
      bwl		      "21"
      bwr		      "0"
      altrlsb		      "11"
      RoundTypeAltr	      "Round"
      PipelineAltr	      on
      HDLInputPortsMappingAltera "xin.21.0.s"
      HDLOutputPortsMappingAltera "yout.10.0.s"
      HDLImplicitPortsMappingAltera "clock.clock, sclr.sclr"
      HDLParameterMappingAltera	"widthin.21.natural,widthout.10.natural,bround"
".1.natural,lpm_representation.\"SIGNED\".natural,pipeline.1.string"
      HDLLibraryInformationAltera "library dspbuilder;use dspbuilder.dspbuilde"
"rblock.all;"
      HDLComponentNameAltera  "sRounderAltr"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope1"
      Ports		      [2]
      Position		      [925, 316, 955, 349]
      Location		      [5, 54, 1029, 741]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      SaveName		      "ScopeData1"
      DataFormat	      "StructureWithTime"
      MaxDataPoints	      "7000"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope2"
      Ports		      [2]
      Position		      [315, 111, 345, 144]
      Location		      [5, 54, 1029, 741]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      DataFormat	      "StructureWithTime"
      MaxDataPoints	      "7000"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [584, 103, 653, 150]
      ForegroundColor	      "blue"
      SourceBlock	      "Altelink/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "c:\\dsp_biulder_demo\\fir_core"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
      JTAGCable		      "USB-Blaster [USB-0]"
      dspb_ver		      "5.1"
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Wave"
      Ports		      [0, 1]
      Position		      [15, 405, 85, 465]
      SineType		      "Sample based"
      Amplitude		      "100"
      Samples		      "100"
      SampleTime	      "8"
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Wave1"
      Ports		      [0, 1]
      Position		      [35, 95, 110, 165]
      SineType		      "Sample based"
      Amplitude		      "64"
      Samples		      "200"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Wave2"
      Ports		      [0, 1]
      Position		      [40, 229, 115, 301]
      SineType		      "Sample based"
      Amplitude		      "64"
      Samples		      "13"
      SampleTime	      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Single Pulse "
      Ports		      [0, 1]
      Position		      [200, 514, 260, 536]
      ForegroundColor	      "blue"
      SourceBlock	      "gate_alteradspbuilder/Single Pulse "
      SourceType	      "HDLEntity AlteraBlockSet"
      SignalGenerationType    "Step   (1 to 0)"
      UseControlInputs	      off
      Impulsewidth	      "1"
      Impulsedelay	      "1"
      StepDelay		      "1"
      ntsamp		      "-1"
      HDLInputPortsMappingAltera "NOINPUT"
      HDLOutputPortsMappingAltera "q.1.0.b"
      HDLImplicitPortsMappingAltera "clock.clock, ena.VCC, sclr.sclr"
      HDLParameterMappingAltera	"StepDelay.1.natural,direction.0.natural"
      HDLLibraryInformationAltera "library dspbuilder;use dspbuilder.dspbuilde"
"rblock.all;"
      HDLComponentNameAltera  "sStepAltr"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      Ports		      [2, 1]
      Position		      [120, 425, 140, 445]
      ShowName		      off
      IconShape		      "round"
      Inputs		      "|++"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay"
      Position		      [165, 409, 230, 471]
    }
    Block {
      BlockType		      Reference
      Name		      "fir32a"
      Ports		      [2, 3]
      Position		      [360, 386, 640, 474]
      ForegroundColor	      "gray"
      DropShadow	      on
      SourceBlock	      "MegaCoreAltr/fir_compiler"
      SourceType	      "HDLEntity AlteraBlockSet"
      altr_type		      "altr_megacore"
      flow_dir		      "d:\\altera\\megacore\\fir_compiler-v3.3.0\\lib"
"\\../../common/ip_toolbench/v1.2.11/bin"
      core_dir		      "d:\\altera\\megacore\\fir_compiler-v3.3.0\\lib"
"\\ip_toolbench"
      core_name		      "fir_compiler"
      core_version	      "3.3.0"
      vofile		      "DSPBuilder_fir32\\fir32a.vo"
      xmlmapfile	      "D:\\altera\\DSPBuilder\\Altlib\\SimgenCMap.xml"
      wizard		      "fir_compiler"
      NewVariation	      off
      VhdlVariationName	      "fir32a.vhd"
      VhdlVariationDate	      "27-Jun-2006 17:56:44"
      n_input_port	      "2"
      n_output_port	      "3"
      array_input	      "data_in rst "
      array_output	      "done fir_result rdy_to_ld "
      clockname		      "clk"
      inptbwl		      "8 1 "
      inptbwr		      " 0 0"
      inptype		      "sb"
      outptbwl		      "1 21 1 "
      outptbwr		      "0 0 0"
      outptype		      "bsb"
      dspbuilder_path	      "D:\\altera\\DSPBuilder\\Altlib"
      HDLInputPortsMappingAltera "data_in.8.0.s, rst.1.0.b"
      HDLOutputPortsMappingAltera "done.1.0.b, fir_result.21.0.s, rdy_to_ld.1."
"0.b"
      HDLImplicitPortsMappingAltera "clk.clock"
      HDLParameterMappingAltera	"NOHDLPARAMETER"
      HDLLibraryInformationAltera "ADD_COMPONENT_SECTION"
      HDLComponentNameAltera  "fir32a"
      HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_fir32/fir32a_add.tcl"
"\";"
    }
    Line {
      SrcBlock		      "Sum"
      SrcPort		      1
      Points		      [0, 5]
      DstBlock		      "Unit Delay"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Sine Wave"
      SrcPort		      1
      DstBlock		      "Sum"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Random\nNumber"
      SrcPort		      1
      Points		      [15, 0; 0, -65]
      DstBlock		      "Sum"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Sine Wave1"
      SrcPort		      1
      Points		      [110, 0; 0, 10]
      Branch {
	Points			[0, 50]
	DstBlock		"Add"
	DstPort			1
      }
      Branch {
	Points			[0, -5]
	DstBlock		"Scope2"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Sine Wave2"
      SrcPort		      1
      Points		      [55, 0]
      Branch {
	Points			[50, 0; 0, -50]
	DstBlock		"Add"
	DstPort			2
      }
      Branch {
	Points			[0, -145]
	DstBlock		"Scope2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Single Pulse "
      SrcPort		      1
      Points		      [35, 0; 0, -70]
      DstBlock		      "fir32a"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Add"
      SrcPort		      1
      Points		      [60, 0]
      Branch {
	Points			[0, 95; -155, 0; 0, 110]
	DstBlock		"Input"
	DstPort			1
      }
      Branch {
	Points			[195, 0; 0, 50]
	Branch {
	  Points		  [0, 70]
	  DstBlock		  "Scope1"
	  DstPort		  1
	}
	Branch {
	  DstBlock		  "P2"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "Input"
      SrcPort		      1
      DstBlock		      "fir32a"
      DstPort		      1
    }
    Line {
      SrcBlock		      "fir32a"
      SrcPort		      2
      Points		      [5, 0; 0, 10]
      DstBlock		      "Rou5"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Rou5"
      SrcPort		      1
      DstBlock		      "Output"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output"
      SrcPort		      1
      Points		      [10, 0; 0, -30]
      Branch {
	Points			[0, -70]
	DstBlock		"Scope1"
	DstPort			2
      }
      Branch {
	DstBlock		"P1"
	DstPort			1
      }
    }
    Annotation {
      Position		      [584, 505]
    }
    Annotation {
      Position		      [388, 171]
    }
    Annotation {
      Position		      [834, 505]
    }
  }
}