📄 fir32a.vhd
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-- megafunction wizard: %FIR Compiler v3.3.0%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- fir32a_st
-- ============================================================
-- Generated by FIR Compiler 3.3.0 [Altera, IP Toolbench v1.2.11 build48]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY fir32a IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
fir_result : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
done : OUT STD_LOGIC;
rdy_to_ld : OUT STD_LOGIC
);
END fir32a;
ARCHITECTURE SYN OF fir32a IS
attribute altera_attribute : string;
attribute altera_attribute of SYN: ARCHITECTURE is "suppress_da_rule_internal=z100";
COMPONENT fir32a_st
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
fir_result : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
done : OUT STD_LOGIC;
rdy_to_ld : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
fir32a_st_inst : fir32a_st
PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
fir_result => fir_result,
done => done,
rdy_to_ld => rdy_to_ld
);
END SYN;
-- =========================================================
-- FIR Compiler Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="FIR Compiler MegaCore Function" version="3.3.0" iptb_version="v1.2.11 build48" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass" active_core="fir32a_st" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "use_mem" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_type" value="M512" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_rate" value="Single Rate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_factor" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_type" value="Auto" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_factor" value="8476.445896323763" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_bit_width" value="10" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_input_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_number_system" value="Signed Binary" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "input_bit_width" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bit_width_method" value="Actual Coefficients" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_number_system" value="Full Resolution" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bit_width" value="21" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bits_right_of_binary_point" value="16" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bits_removed_from_lsb" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_lsb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_msb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_input" value="Slave Sink" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_output" value="Master Source" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "device_family" value="Cyclone" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "structure" value="Distributed Arithmetic : Fully Parallel Filter" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pipeline_level" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "clocks_to_compute" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_serial_units" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "data_storage" value="Logic Cells" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_storage" value="M4K" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "multiplier_storage" value="Logic Cells" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "force_non_symmetric_structure" value="0" type="BOOLEAN" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficients_reload" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficients_reload_sgl_clock" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "max_clocks_to_compute" value="4" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "set_1" value="Low Pass Set, Floating, Low Pass, Hanning, 32, 3900000.0, 119000.0, 3750000.0, 0, 3.562E-5, 2.9399E-4, 0.00101508, 0.00243167, 0.00473829, 0.0080622, 0.0124401, 0.0178034, 0.0239746, 0.0306755, 0.0375464, 0.0441754, 0.0501346, 0.0550193, 0.0584858, 0.0602847, 0.0602847, 0.0584858, 0.0550193, 0.0501346, 0.0441754, 0.0375464, 0.0306755, 0.0239746, 0.0178034, 0.0124401, 0.0080622, 0.00473829, 0.00243167, 0.00101508, 2.9399E-4, 3.562E-5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "number_of_sets" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bit_width" value="21" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bits_right_of_binary_point" value="16" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "logic_cell" value="679" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m512" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m4k" value="27" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "megaram" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dsp_block" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "throughput" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "memory_units" value="3" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "matlab_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_simulation_clock_period" value="10.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_OPTIMIZATION=ALL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="fir32a.vo" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
-- RELATED_FILES: fir32a.vhd, fir32a_st.v, fir32a_constraints.tcl, fir32a_st.v, fir32a.vhd;
-- IPFS_FILES: fir32a.vo;
-- =========================================================
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