fir32altblk.xml

fir滤波器

<fir32>
<dspbuilder_info>
	<dspbuilder_version>5.1</dspbuilder_version>
	<dspbuilder_build_number>Build 176</dspbuilder_build_number>
	<dspbuilder_build_date>10/26/2005</dspbuilder_build_date>
	<toplevel_design_name>fir32</toplevel_design_name>
	<date_stamp>20060627184754</date_stamp>
</dspbuilder_info>
   <block_dspbuilder>
      <db_block>
         <instancename>Input</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>1</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>fir32a</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Output</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>2</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>10</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Rou5</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Rou5</instancename>
         <sourcename>HDLEntityAlteraBlockSet</sourcename>
         <instancenumber>3</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>21</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>HDLInputPortsMappingAltera</pname>
            <pvalue>xin.21.0.s</pvalue>
            <pname>HDLOutputPortsMappingAltera</pname>
            <pvalue>yout.10.0.s</pvalue>
            <pname>HDLImplicitPortsMappingAltera</pname>
            <pvalue>clock.clock,sclr.sclr</pvalue>
            <pname>HDLParameterMappingAltera</pname>
            <pvalue>widthin.21.natural,widthout.10.natural,bround.1.natural,lpm_representation."SIGNED".natural,pipeline.1.string</pvalue>
            <pname>HDLLibraryInformationAltera</pname>
            <pvalue>librarydspbuilder;usedspbuilder.dspbuilderblock.all;</pvalue>
            <pname>HDLComponentNameAltera</pname>
            <pvalue>sRounderAltr</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir32a</srcblk>
            <srcport>2</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Output</dstblk>
         </port_db>
         <nparameter>10</nparameter>
      </db_block>
      <db_block>
         <instancename>SinglePulse</instancename>
         <sourcename>HDLEntityAlteraBlockSet</sourcename>
         <instancenumber>4</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>HDLInputPortsMappingAltera</pname>
            <pvalue>NOINPUT</pvalue>
            <pname>HDLOutputPortsMappingAltera</pname>
            <pvalue>q.1.0.b</pvalue>
            <pname>HDLImplicitPortsMappingAltera</pname>
            <pvalue>clock.clock,ena.VCC,sclr.sclr</pvalue>
            <pname>HDLParameterMappingAltera</pname>
            <pvalue>StepDelay.1.natural,direction.0.natural</pvalue>
            <pname>HDLLibraryInformationAltera</pname>
            <pvalue>librarydspbuilder;usedspbuilder.dspbuilderblock.all;</pvalue>
            <pname>HDLComponentNameAltera</pname>
            <pvalue>sStepAltr</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>fir32a</dstblk>
         </port_db>
         <nparameter>7</nparameter>
      </db_block>
      <db_block>
         <instancename>fir32a</instancename>
         <sourcename>HDLEntityAlteraBlockSet</sourcename>
         <instancenumber>5</instancenumber>
         <inport>2</inport>
         <outport>3</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>HDLInputPortsMappingAltera</pname>
            <pvalue>data_in.8.0.s,rst.1.0.b</pvalue>
            <pname>HDLOutputPortsMappingAltera</pname>
            <pvalue>done.1.0.b,fir_result.21.0.s,rdy_to_ld.1.0.b</pvalue>
            <pname>HDLImplicitPortsMappingAltera</pname>
            <pvalue>clk.clock</pvalue>
            <pname>HDLParameterMappingAltera</pname>
            <pvalue>NOHDLPARAMETER</pvalue>
            <pname>HDLLibraryInformationAltera</pname>
            <pvalue>ADD_COMPONENT_SECTION</pvalue>
            <pname>HDLComponentNameAltera</pname>
            <pvalue>fir32a</pvalue>
            <pname>HDLComponentQuartusTclScript</pname>
            <pvalue>"$workdir/DSPBuilder_fir32/fir32a_add.tcl";</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Input</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>SinglePulse</srcblk>
            <srcport>1</srcport>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Rou5</dstblk>
         </port_db>
         <nparameter>8</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>2000</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>0</nsubsystem>
      <nblocks>5</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Stratix</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>c:\dsp_biulder_demo\fir_core</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>1</bContainMegaCoreIpTb>
   </top_signalcompiler>
</fir32>