📄 fir32blockinfosframeright.html
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<p><a name ="Input"></a></p>
<TABLE>
<TR><TD> Block instance name </TD><TD><b><font color="blue">Input</font></b></TD></TR>
<TR><TD> Block type </TD><TD>altbus</TD></TR>
<TR><TD> Simulation sampling period value </TD><TD>1e+009 ns</TD></TR>
<TR><TD>Port Section</TD></TR><TR><TD></TD><TD>
<TABLE ><TR><TD ALIGN="left" COLSPAN="2"> 1 Output Port </TD></TR><TR>
<TD></TD>
<TD>O1 is driving a bus<font size="-1"> [8].[0]</font></TD>
</TR>
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</TD>
</TR><br><br></TABLE>
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<p><a name ="Output"></a></p>
<TABLE>
<TR><TD> Block instance name </TD><TD><b><font color="blue">Output</font></b></TD></TR>
<TR><TD> Block type </TD><TD>altbus</TD></TR>
<TR><TD> Simulation sampling period value </TD><TD>1e+009 ns</TD></TR>
<TR><TD>Port Section</TD></TR><TR><TD></TD><TD>
<TABLE ><TR><TD ALIGN="left" COLSPAN="2"> 1 Input Port </TD></TR><TR>
<TD></TD>
<TR><TD ALIGN="left" COLSPAN="2"> 1 Output Port </TD></TR><TR>
<TD></TD>
<TD>O1 is driving a bus<font size="-1"> [10].[0]</font></TD>
</TR>
</TABLE>
</TD>
</TR><br><br></TABLE>
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<p><a name ="Rou5"></a></p>
<TABLE>
<TR><TD> Block instance name </TD><TD><b><font color="blue">Rou5</font></b></TD></TR>
<TR><TD> Block type </TD><TD>hdlentity</TD></TR>
<TR><TD> Simulation sampling period value </TD><TD>1e+009 ns</TD></TR>
<TR><TD>Port Section</TD></TR><TR><TD></TD><TD>
<TABLE ><TR><TD ALIGN="left" COLSPAN="2"> 1 Input Port </TD></TR><TR>
<TD></TD>
<TD>I1 is driven by a bus<font size="-1"> [21].[0]</font></TD>
</TR>
<TR><TD ALIGN="left" COLSPAN="2"> 1 Output Port </TD></TR><TR>
<TD></TD>
<TD>O1 is driving a bus<font size="-1"> [10].[0]</font></TD>
</TR>
</TABLE>
</TD>
</TR><br><br></TABLE>
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<p><a name ="SinglePulse"></a></p>
<TABLE>
<TR><TD> Block instance name </TD><TD><b><font color="blue">SinglePulse</font></b></TD></TR>
<TR><TD> Block type </TD><TD>hdlentity</TD></TR>
<TR><TD> Simulation sampling period value </TD><TD>1e+009 ns</TD></TR>
<TR><TD>Port Section</TD></TR><TR><TD></TD><TD>
<TABLE ><TR><TD ALIGN="left" COLSPAN="2"> 1 Output Port </TD></TR><TR>
<TD></TD>
<TD>O1 is driving a bus<font size="-1"> [1].[0]</font></TD>
</TR>
</TABLE>
</TD>
</TR><br><br></TABLE>
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<p><a name ="fir32a"></a></p>
<TABLE>
<TR><TD> Block instance name </TD><TD><b><font color="blue">fir32a</font></b></TD></TR>
<TR><TD> Block type </TD><TD>hdlentity</TD></TR>
<TR><TD> Simulation sampling period value </TD><TD>1e+009 ns</TD></TR>
<TR><TD>Port Section</TD></TR><TR><TD></TD><TD>
<TABLE ><TR><TD ALIGN="left" COLSPAN="2"> 2 Input Port </TD></TR><TR>
<TD></TD>
<TD>I1 is driven by a bus<font size="-1"> [8].[0]</font></TD>
</TR>
<TR>
<TD></TD>
<TD>I2 is driven by a bus<font size="-1"> [1].[0]</font></TD>
</TR>
<TR><TD ALIGN="left" COLSPAN="2"> 3 Output Port </TD></TR><TR>
<TD></TD>
<TD>O1 is driving a bus<font size="-1"> [1].[0]</font></TD>
</TR>
<TR>
<TD></TD>
<TD>O2 is driving a bus<font size="-1"> [21].[0]</font></TD>
</TR>
<TR>
<TD></TD>
<TD>O3 is driving a bus<font size="-1"> [1].[0]</font></TD>
</TR>
</TABLE>
</TD>
</TR><br><br></TABLE>
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<p><a name ="blinf"></a> The Block Information Table provides bit width information for input and output ports of the DSP Builder blocks used in the design <b>fir32<p><i> Bit width information </i><p>.mdl </b> . The following notation is used:<br><br> <b> Simulink Block Name (VHDL Instance Name) :</b><br>
<b> i(Input port number) [L].[R]</b><br>
<b> o(Output port number) [L].[R]</b><br><br>[L] is the number of bit on the left side of the binary point. [R] is the number of bit on the right side of the binary point. [L].[R] Simulink signal is mapped to the signal type std_logic_vector(L+R-1 downto 0)
from VHDL library package ieee.std_logic_1164.all. [R]=0 when the bus type is <i>Signed Integer</i> or <i>Unsigned Integer</i>. The most significant bit of the bus is the sign bit when the bus type is <i>Signed Integer</i> or <i>Signed Binary Fractional</i><p><i>Simulation sampling period value </i><p><p>The Simulation sampling period value is the value that Simulink uses to simulate the block.In order to maintain cycle accuracy between Simulink and HDL simulation, it's important to verify that the clock domains of the hardware design matches the sampling frequencyFor Designs using the altera PLL block, the Simulation sampling period value should match the PLL output value.For Designs which are not using PLL blocks, each Simulation sampling period value of all blocks should be equal to the clock value used in hardware.</p><p>Copyright © 2001-2003 Altera Corporation. All rights reserved.</p><br></p><hr><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br>
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