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</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - FIR Compiler MegaCore Function v3.3.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>fir32a_st</TD></TR><TR><TD><B>Variation Name</B></TD><TD>fir32a</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>c:\dsp_biulder_demo\sin_cos_modem</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>fir32a.vhd</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>fir32a.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>fir32a.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>fir32a_st.v</TD><TD>Generated FIR Filter Netlist. This file is required for Quartus II synthesis. It will be added to your current Quartus II project.</TD></TR><TR><TD>fir32a_constraints.tcl</TD><TD>Constraints setting file for Quartus II synthesis. This file contains the necessary constraints to achieve FIR Filter size and speed.</TD></TR><TR><TD>fir32a_coef_[0..2].hex</TD><TD>Memory initialization files. These files are required both for simulation with IP Functional Simulation Models and for Synthesis using the Quartus II software.</TD></TR><TR><TD>fir32a_mlab.m</TD><TD>A MATLAB M-File. This file provides a MATLAB simulation model for the customized FIR Variant.</TD></TR><TR><TD>tb_fir32a.m</TD><TD>A MATLAB M-File. This file provides a MATLAB testbench for the customized FIR Variant.</TD></TR><TR><TD>fir32a.vec</TD><TD>Quartus II Vector file. This file provides simulation test vectors to be used simulating the customized FIR Variant with the Quartus II software.</TD></TR><TR><TD>tb_fir32a.v</TD><TD>A verilog HDL file. This file provides a verilog HDL testbench for the customized FIR Variant.</TD></TR><TR><TD>fir32a_data_in.txt</TD><TD>A text file. This file provides an impulse simulation data file for Matlab or Verilog HDL testbench.</TD></TR><TR><TD>fir32a_param.txt</TD><TD>A text file. This file record all output parameters for customized FIR variant.</TD></TR><TR><TD>fir32a_silent_param.txt</TD><TD>A text file. This file record all input parameters for customized FIR variant.</TD></TR><TR><TD>fir32a_coef_int.txt</TD><TD>A text file. This file record fixed point coefficients.</TD></TR><TR><TD>fir32a.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rst</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>data_in</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>fir_result</TD><TD>OUTPUT</TD><TD>21</TD></TR><TR><TD>done</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>rdy_to_ld</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
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