fir_compiler_simgen_vho.tcl

fir滤波器

if {[file exist [project env]] > 0} {project close}
if {[file exist "fir_compiler.mpf"] == 0} {
	project new . fir_compiler fir_compiler
} else {
project open fir_compiler
}
if {[file exist work] ==0} 	{
  exec vlib work
  exec vmap work work
}
if {[file exist lpm] ==0} 	{ 
  exec vlib lpm 
  exec vmap lpm lpm}
vcom -93 -work lpm d:/altera/quartus51/eda/sim_lib/220pack.vhd 
vcom -93 -work lpm d:/altera/quartus51/eda/sim_lib/220model.vhd 
if {[file exist altera_mf] ==0} 	{ 
  exec vlib altera_mf 
  exec vmap altera_mf altera_mf}
vcom -93 -work altera_mf d:/altera/quartus51/eda/sim_lib/altera_mf_components.vhd 
vcom -93 -work altera_mf d:/altera/quartus51/eda/sim_lib/altera_mf.vhd 
if {[file exist sgate] ==0} 	{ 
  exec vlib sgate 
  exec vmap sgate sgate} 
vcom -93 -work sgate d:/altera/quartus51/eda/sim_lib/sgate_pack.vhd  
vcom -93 -work sgate d:/altera/quartus51/eda/sim_lib/sgate.vhd 
vcom -93 fir_compiler.vho 
vlog -work work tb_fir_compiler.v
vsim  tb_fir_compiler -t 1ps 
run 500000000 ns